- 您现在的位置：买卖IC网 > PDF目录20640 > ADE7753ARSZ (Analog Devices Inc)IC ENERGY METERING 1PHASE 20SSOP PDF资料下载
参数资料
| 型号： | ADE7753ARSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/60页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METERING 1PHASE 20SSOP |
| 标准包装： | 66 |
| 输入阻抗： | 390 千欧 |
| 测量误差： | 0.1% |
| 电压 - 高输入/输出： | 2.4V |
| 电压 - 低输入/输出： | 0.8V |
| 电流 - 电源： | 3mA |
| 电源电压： | 4.75 V ~ 5.25 V |
| 测量仪表类型： | 单相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 管件 |
| 产品目录页面： | 797 (CN2011-ZH PDF) |
| 配用： | EVAL-ADE7753ZEB-ND - BOARD EVALUATION AD7753 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页当前第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页
ADE7753
V 2
CHANNEL 2
FULL SCALE
SAGLVL [7:0]
SAG
SAGCYC [7:0] = 0x04
3 LINE CYCLES
SAG RESET HIGH
WHEN CHANNEL 2
EXCEEDS SAGLVL [7:0]
VPKLVL[7:0]
PKV INTERRUPT
FLAG (BIT 8 OF
STATUS REGISTER)
READ RSTSTATUS
PKV RESET LOW
WHEN RSTSTATUS
REGISTER IS READ
02875-0-043
REGISTER
02875-0-088
Figure 43. ADE7753 Sag Detection
set in the sag level register (SAGLVL[7:0]) for three line cycles.
The quantities 0 and 1 are not valid for the SAGCYC register,
and the contents represent one more than the desired number
of full line cycles. For example, when the sag cycle (SAGCYC[7:0])
contains 0x04, the SAG pin goes active low at the end of the
third line cycle for which the line voltage (Channel 2 signal)
falls below the threshold, if the DISSAG bit in the mode register
is Logic 0. As is the case when zero crossings are no longer
detected, the sag event is also recorded by setting the SAG flag
in the interrupt status register. If the SAG enable bit is set to
Logic 1, the IRQ logic output goes active low—see the ADE7753
Interrupts section. The SAG pin goes logic high again when the
absolute value of the signal on Channel 2 exceeds the sag level
set i n the sag level register. This is shown in Figure 43 when the
SAG pin goes high again during the fifth line cycle from the
time when the signal on Channel 2 first dropped below the
threshold level.
Sag Level Set
The contents of the sag level register (1 byte) are compared to
the absolute value of the most significant byte output from LPF1
after it is shifted left by one bit, thus, for example, the nominal
maximum code from LPF1 with a full-scale signal on Channel 2
is 0x2518—see the Channel 2 Sampling section. Shifting one bit
left gives 0x4A30. Therefore writing 0x4A to the SAG level
register puts the sag detection level at full scale. Writing 0x00 or
0x01 puts the sag detection level at 0. The SAG level register is
compared to the most significant byte of a waveform sample
after the shift left and detection is made when the contents of
the sag level register are greater.
PEAK DETECTION
The ADE7753 can also be programmed to detect when the
absolute value of the voltage or current channel exceeds a
specified peak value. Figure 44 illustrates the behavior of the
peak detection for the voltage channel. Both Channel 1 and
Figure 44. ADE7753 Peak Level Detection
in the voltage peak register (VPKLVL[7:0]). The voltage peak
event is recorded by setting the PKV flag in the interrupt status
register. If the PKV enable bit is set to Logic 1 in the interrupt
mask register, the IRQ logic output goes active low. Similarly,
the current peak event is recorded by setting the PKI flag in the
interrupt status register—see the ADE7753 Interrupts section.
Peak Level Set
The contents of the VPKLVL and IPKLVL registers are
respectively compared to the absolute value of Channel 1 and
Channel 2 after they are multiplied by 2. Thus, for example, the
nominal maximum code from the Channel 1 ADC with a full-
scale signal is 0x2851EC—see the Channel 1 Sampling section.
Multiplying by 2 gives 0x50A3D8. Therefore, writing 0x50 to
the IPKLVL register, for example, puts the Channel 1 peak
detection level at full scale and sets the current peak detection
to its least sensitive value. Writing 0x00 puts the Channel 1
detection level at 0. The detection is done by comparing the
contents of the IPKLVL register to the incoming Channel 1
sample. The IRQ pin indicates that the peak level is exceeded if
the PKI or PKV bits are set in the interrupt enable register
(IRQEN[15:0]) at Address 0x0A.
Peak Level Record
The ADE7753 records the maximum absolute value reached by
Channel 1 and Channel 2 in two different registers—IPEAK
and VPEAK, respectively. VPEAK and IPEAK are 24-bit
unsigned registers. These registers are updated each time the
absolute value of the waveform sample from the corresponding
channel is above the value stored in the VPEAK or IPEAK
register. The contents of the VPEAK register correspond to 2×
the maximum absolute value observed on the Channel 2 input.
The contents of IPEAK represent the maximum absolute value
observed on the Channel 1 input. Reading the RSTVPEAK and
RSTIPEAK registers clears their respective contents after the read
operation.
Channel 2 are monitored at the same time.
Rev. C | Page 20 of 60
相关PDF资料 |
PDF描述 |
|---|---|
| A7SSB-1506G | CABLE D-SUB-AFM15B/AE15G/AFM15B |
| HMM06DSUS | CONN EDGECARD 12POS .156 DIP SLD |
| GCC10DCAI-S189 | CONN EDGECARD 20POS R/A .100 SLD |
| ADE7759ARSZ | IC ENERGY METERING 1PHASE 20SSOP |
| RMM40DTAD-S189 | CONN EDGECARD 80POS R/A .156 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADE7753ARSZ | 制造商:Analog Devices 功能描述:ENERGY METERING IC |
| ADE7753ARSZ | 制造商:Analog Devices 功能描述:IC MULTIFUNCTION METER |
| ADE7753ARSZRL | 功能描述:IC ENERGY METERING 1PHASE 20SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:* |
| ADE7753-ARSZRL | 制造商:Analog Devices 功能描述: |
| ADE7753XRS | 制造商:Analog Devices 功能描述: |
发布紧急采购，3分钟左右您将得到回复。