参数资料
型号: ADE7753ARSZ
厂商: Analog Devices Inc
文件页数: 57/60页
文件大小: 0K
描述: IC ENERGY METERING 1PHASE 20SSOP
标准包装: 66
输入阻抗: 390 千欧
测量误差: 0.1%
电压 - 高输入/输出: 2.4V
电压 - 低输入/输出: 0.8V
电流 - 电源: 3mA
电源电压: 4.75 V ~ 5.25 V
测量仪表类型: 单相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-SSOP(0.209",5.30mm 宽)
供应商设备封装: 20-SSOP
包装: 管件
产品目录页面: 797 (CN2011-ZH PDF)
配用: EVAL-ADE7753ZEB-ND - BOARD EVALUATION AD7753
ADE7753
INTERRUPT STATUS REGISTER (0x0B), RESET INTERRUPT STATUS REGISTER (0x0C),
INTERRUPT ENABLE REGISTER (0x0A)
The status register is used by the MCU to determine the source of an interrupt request (IRQ). When an interrupt event occurs in the
ADE7753, the corresponding flag in the interrupt status register is set to logic high. If the enable bit for this flag is Logic 1 in the interrupt
enable register, the IRQ logic output goes active low. When the MCU services the interrupt, it must first carry out a read from the
interrupt status register to determine the source of the interrupt.
Table 15. Interrupt Status Register, Reset Interrupt Status Register, and Interrupt Enable Register
Bit Location
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Interrupt Flag
AEHF
SAG
CYCEND
WSMP
ZX
TEMP
RESET
AEOF
PKV
PKI
VAEHF
VAEOF
ZXTO
PPOS
PNEG
RESERVED
Description
Indicates that an interrupt occurred because the active energy register, AENERGY, is more than half full.
Indicates that an interrupt was caused by a SAG on the line voltage.
Indicates the end of energy accumulation over an integer number of half line cycles as defined by
the content of the LINECYC register—see the Line Cycle Energy Accumulation Mode section.
Indicates that new data is present in the waveform register.
This status bit is set to Logic 0 on the rising and falling edge of the the voltage waveform.
See the Zero-Crossing Detection section.
Indicates that a temperature conversion result is available in the temperature register.
Indicates the end of a reset (for both software or hardware reset). The corresponding enable bit has no
function in the interrupt enable register, i.e., this status bit is set at the end of a reset, but it cannot
be enabled to cause an interrupt.
Indicates that the active energy register has overflowed.
Indicates that waveform sample from Channel 2 has exceeded the VPKLVL value.
Indicates that waveform sample from Channel 1 has exceeded the IPKLVL value.
Indicates that an interrupt occurred because the active energy register, VAENERGY, is more than half full.
Indicates that the apparent energy register has overflowed.
Indicates that an interrupt was caused by a missing zero crossing on the line voltage for the specified
number of line cycles—see the Zero-Crossing Timeout section.
Indicates that the power has gone from negative to positive.
Indicates that the power has gone from positive to negative.
Reserved.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADDR: 0x0A, 0x0B, 0x0C
RESERVED
PNEG
(POWER POSITIVE TO NEGATIVE)
PPOS
(POWER NEGATIVE TO POSITIVE)
ZXTO
(ZERO-CROSSING TIMEOUT)
VAEOF
(VAENERGY OVERFLOW)
VAEHF
(VAENERGY IS HALF-FULL)
PK1
(CHANNEL 1 SAMPLE ABOVE IPKLVL)
PKV
(CHANNEL 2 SAMPLE ABOVE VPKLVL)
Figure 96. Interrupt Status/Interrupt Enable Register
Rev. C | Page 57 of 60
AEHF
(ACTIVE ENERGY HALF-FULL)
SAG
(SAG ONLINE VOLTAGE)
CYCEND
(END OF LINECYC HALF LINE CYCLES)
WSMP
(WAVEFORM SAMPLES DATA READY)
ZX
(ZERO CROSSING)
TEMPL
(TEMPERATURE DATA READY)
RESET
(END OF SOFTWARE/HARDWARE RESET)
AEOF
(ACTIVE ENERGY REGISTER OVERFLOW)
02875-A-013
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