参数资料
型号: ADE7753ARSZ
厂商: Analog Devices Inc
文件页数: 55/60页
文件大小: 0K
描述: IC ENERGY METERING 1PHASE 20SSOP
标准包装: 66
输入阻抗: 390 千欧
测量误差: 0.1%
电压 - 高输入/输出: 2.4V
电压 - 低输入/输出: 0.8V
电流 - 电源: 3mA
电源电压: 4.75 V ~ 5.25 V
测量仪表类型: 单相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-SSOP(0.209",5.30mm 宽)
供应商设备封装: 20-SSOP
包装: 管件
产品目录页面: 797 (CN2011-ZH PDF)
配用: EVAL-ADE7753ZEB-ND - BOARD EVALUATION AD7753

ADE7753
ADE7753 REGISTER DESCRIPTIONS
All ADE7753 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the communications register
and then transferring the register data. A full description of the serial interface protocol is given in the ADE7753 Serial Interface section.
COMMUNICATIONS REGISTER
The communications register is an 8-bit, write-only register which controls the serial data transfer between the ADE7753 and the host
processor. All data transfer operations must begin with a write to the communications register. The data written to the communications
register determines whether the next operation is a read or a write and which register is being accessed. Table 13 outlines the bit
designations for the communications register.
DB7
W/R
DB6
0
DB5
A5
DB4
A4
DB3
A3
DB2
A2
DB1
A1
DB0
A0
Table 13. Communications Register
Bit Location
0 to 5
6
7
Bit Mnemonic
A0 to A5
RESERVED
W/R
Description
The six LSBs of the communications register specify the register for the data transfer operation.
Table 12 lists the address of each ADE7753 on-chip register.
This bit is unused and should be set to 0.
When this bit is a Logic 1, the data transfer operation immediately following the write to the
communications register is interpreted as a write to the ADE7753.
When this bit is a Logic 0, the data transfer operation immediately following the write to the
communications register is interpreted as a read operation.
MODE REGISTER (0x09)
The ADE7753 functionality is configured by writing to the mode register. Table 14 describes the functionality of each bit in the register.
Table 14. Mode Register
Default
Bit Location
0
1
2
3
4
Bit Mnemonic
DISHPF
DISLPF2
DISCF
DISSAG
ASUSPEND
Value
0
0
1
1
0
Description
HPF (high-pass filter) in Channel 1 is disabled when this bit is set.
LPF (low-pass filter) after the multiplier (LPF2) is disabled when this bit is set.
Frequency output CF is disabled when this bit is set.
Line voltage sag detection is disabled when this bit is set.
By setting this bit to Logic 1, both ADE7753 A/D converters can be turned off.
In normal operation, this bit should be left at Logic 0. All digital functionality can be
stopped by suspending the clock signal at CLKIN pin.
5
TEMPSEL
0
Temperature conversion starts when this bit is set to 1. This bit is automatically reset to 0
when the temperature conversion is finished.
6
SWRST
0
Software Chip Reset. A data transfer should not take place to the ADE7753 for at least
18 μs after a software reset.
7
8
9
10
CYCMODE
DISCH1
DISCH2
SWAP
0
0
0
0
Setting this bit to Logic 1 places the chip into line cycle energy accumulation mode.
ADC 1 (Channel 1) inputs are internally shorted together.
ADC 2 (Channel 2) inputs are internally shorted together.
By setting this bit to Logic 1 the analog inputs V2P and V2N are connected to ADC 1 and
the analog inputs V1P and V1N are connected to ADC 2.
12, 11
DTRT1, 0
00
These bits are used to select the waveform register update rate.
DTRT 1
DTRT0
Update Rate
0
0
27.9 kSPS (CLKIN/128)
0
1
14 kSPS (CLKIN/256)
1
0
7 kSPS (CLKIN/512)
1
1
3.5 kSPS (CLKIN/1024)
Rev. C | Page 55 of 60
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