参数资料
型号: ADSP-BF504KCPZ-4F
厂商: Analog Devices Inc
文件页数: 27/80页
文件大小: 0K
描述: IC CCD SIGNAL PROCESSOR 88LFCSP
视频文件: Blackfin? BF50x Processor Family
标准包装: 1
系列: Blackfin®
类型: 定点
接口: CAN,EBI/EMI,I²C,IrDA,PPI,SPI,SPORT,UART/USART
时钟速率: 400MHz
非易失内存: 闪存(16MB)
芯片上RAM: 68kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.31V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 88-VFQFN 裸露焊盘,CSP
供应商设备封装: 88-LFCSP(12x12)
包装: 托盘
Rev. A
|
Page 33 of 80
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July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Table 25. Clock Out Timing
Parameter
V
DDEXT = 1.8 V
V
DDEXT = 2.5 V/3.3 V
Min
Max
Min
Max
Unit
Switching Characteristics
tSCLK
CLKOUT1 Period2,3
10
ns
tSCLKH
CLKOUT1 Width High
44ns
tSCLKL
CLKOUT1 Width Low
4
ns
1 The ADSP-BF504/ADSP-BF504F/ADSP-BF506F processor does not have a dedicated CLKOUT pin. Rather, the EXTCLK pin may be programmed to serve as CLKBUF or
CLKOUT. This parameter applies when EXTCLK is programmed to output CLKOUT.
2 The tSCLK value is the inverse of the fSCLK specification. Reduced supply voltages affect the best-case value of 10 ns listed here.
3 The tSCLK value does not account for the effects of jitter.
Figure 11. Clock Out Timing
t
SCLKL
t
SCLKH
t
SCLK
CLKOUT
Table 26. Power-Up Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
t
RST
_IN_PWR
RESET Deasserted after the V
DDINT, VDDEXT, VDDFLASH, and CLKIN Pins are Stable and
Within Specification
3500 × t
CKIN
ns
In Figure 12, VDD_SUPPLIES is VDDINT, VDDEXT, and VDDFLASH.
Figure 12. Power-Up Reset Timing
RESET
tRST_IN_PWR
CLKIN
V
DD_SUPPLIES
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