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| 型号： | ADSP-TS203SABP-050 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 46/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP FLOAT/FIXED 500MHZ 576BGA |
| 标准包装： | 1 |
| 系列： | TigerSHARC® |
| 类型： | 定点/浮点 |
| 接口： | 主机接口，连接端口，多处理器 |
| 时钟速率： | 500MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 512kB |
| 电压 - 输入/输出： | 2.50V |
| 电压 - 核心： | 1.05V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 576-BBGA 裸露焊盘 |
| 供应商设备封装： | 576-BGA-ED（25x25） |
| 包装： | 托盘 |
| 其它名称： | ADSP-TS203SABP050 ADSP-TS203SABP050-ND |
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Rev. D
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Page 7 of 48
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May 2012
The external port supports a unified address space (see Figure 2)
that enables direct interprocessor accesses of each ADSP-
TS203S processor’s internal memory and registers. The proces-
sor’s on-chip distributed bus arbitration logic provides simple,
glueless connection for systems containing up to eight
ADSP-TS203S processors and a host processor. Bus arbitration
has a rotating priority. Bus lock supports indivisible read-
modify-write sequences for semaphores. A bus fairness feature
prevents one processor from holding the external bus too long.
The processor’s two link ports provide a second path for inter-
processor communications with throughput of 1G byte per
second. The cluster bus provides 500M bytes per second
throughput—with a total of 1.5G bytes per second interproces-
sor bandwidth.
SDRAM Controller
The SDRAM controller controls the processor’s transfers of
data to and from external synchronous DRAM (SDRAM) at a
throughput of 32 bits per SCLK cycle using the external port
and SDRAM control pins.
The SDRAM interface provides a glueless interface with stan-
dard SDRAMs—16M bits, 64M bits, 128M bits, 256M bits and
512M bits. The processor supports directly a maximum of four
banks of 64M words
× 32 bits of SDRAM. The SDRAM inter-
face is mapped in external memory in each processor’s unified
memory map.
EPROM Interface
The processor can be configured to boot from an external 8-bit
EPROM at reset through the external port. An automatic pro-
cess (which follows reset) loads a program from the EPROM
into internal memory. This process uses 16 wait cycles for each
read access. During booting, the BMS pin functions as the
EPROM chip select signal. The EPROM boot procedure uses
DMA Channel 0, which packs the bytes into 32-bit instructions.
Applications can also access the EPROM (write flash memories)
during normal operation through DMA.
The EPROM or flash memory interface is not mapped in the
processor’s unified memory map. It is a byte address space lim-
ited to a maximum of 16M bytes (24 address bits). The EPROM
or flash memory interface can be used after boot via a DMA.
DMA CONTROLLER
The ADSP-TS203S processor’s on-chip DMA controller, with
10 DMA channels, provides zero-overhead data transfers with-
out processor intervention. The DMA controller operates
independently and invisibly to the processor’s core, enabling
DMA operations to occur while the processor’s core continues
to execute program instructions.
The DMA controller performs DMA transfers between internal
memory, external memory, and memory-mapped peripherals;
the internal memory of other DSPs on a common bus, a host
processor, or link port I/O; between external memory and exter-
nal peripherals or link port I/O; and between an external bus
master and internal memory or link port I/O. The DMA con-
troller performs the following DMA operations:
External port block transfers. Four dedicated bidirectional
DMA channels transfer blocks of data between the proces-
sor’s internal memory and any external memory or
memory-mapped peripheral on the external bus. Master
mode and handshake mode protocols are supported.
Link port transfers. Four dedicated DMA channels (two
transmit and two receive) transfer quad-word data only
between link ports and between a link port and internal or
external memory. These transfers only use handshake
mode protocol. DMA priority rotates between the two
receive channels.
AutoDMA transfers. Two dedicated unidirectional DMA
channels transfer data received from an external bus master
to internal memory or to link port I/O. These transfers only
use slave mode protocol, and an external bus master must
initiate the transfer.
The DMA controller provides these additional features:
Flyby transfers. Flyby operations only occur through the
external port (DMA channel 0) and do not involve the pro-
cessor’s core. The DMA controller acts as a conduit to
transfer data from an external I/O device to external
SDRAM memory. During a transaction, the processor
relinquishes the external data bus; outputs addresses and
memory selects (MSSD3–0); outputs the IORD, IOWR,
IOEN, and RD/WR strobes; and responds to ACK.
DMA chaining. DMA chaining operations enable applica-
tions to automatically link one DMA transfer sequence to
another for continuous transmission. The sequences can
occur over different DMA channels and have different
transmission attributes.
Two-dimensional transfers. The DMA controller can
access and transfer two-dimensional memory arrays on any
DMA transmit or receive channel. These transfers are
implemented with index, count, and modify registers for
both the X and Y dimensions.
LINK PORTS (LVDS)
The processor’s two full-duplex link ports each provide addi-
tional four-bit receive and four-bit transmit I/O capability,
using low-voltage, differential-signal (LVDS) technology. With
the ability to operate at a double data rate—latching data on
both the rising and falling edges of the clock—running at
250 MHz, each link port can support up to 250M bytes per sec-
ond per direction, for a combined maximum throughput of
1G byte per second.
The link ports provide an optional communications channel
that is useful in multiprocessor systems for implementing point-
to-point interprocessor communications. Applications can also
use the link ports for booting.
Each link port has its own triple-buffered quad-word input and
double-buffered quad-word output registers. The processor’s
core can write directly to a link port’s transmit register and read
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-TS203SABP-05X | 制造商:Analog Devices 功能描述: |
| ADSP-TS203SABPZ050 | 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:TigerSHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-TS203SBBPZ050 | 制造商:Analog Devices 功能描述:DSP - Bulk |
| ADSQ-1410 | 制造商:MURATA-PS 制造商全称:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
| ADSQ-1410-C | 制造商:MURATA-PS 制造商全称:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
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