- 您现在的位置：买卖IC网 > PDF目录1900 > ADSP-TS203SABP-050 (Analog Devices Inc)IC DSP FLOAT/FIXED 500MHZ 576BGA PDF资料下载
参数资料
| 型号： | ADSP-TS203SABP-050 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP FLOAT/FIXED 500MHZ 576BGA |
| 标准包装： | 1 |
| 系列： | TigerSHARC® |
| 类型： | 定点/浮点 |
| 接口： | 主机接口，连接端口，多处理器 |
| 时钟速率： | 500MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 512kB |
| 电压 - 输入/输出： | 2.50V |
| 电压 - 核心： | 1.05V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 576-BBGA 裸露焊盘 |
| 供应商设备封装： | 576-BGA-ED（25x25） |
| 包装： | 托盘 |
| 其它名称： | ADSP-TS203SABP050 ADSP-TS203SABP050-ND |
第1页第2页第3页第4页第5页第6页当前第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页
Rev. D
|
Page 15 of 48
|
May 2012
SDA10
O/T
(pu_0)
nc
SDRAM Address Bit 10. Separate A10 signals enable SDRAM refresh operation while
the processor executes non-SDRAM transactions.
SDCKE
I/O/T
(pu_m/
pd_m)
nc
SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or suspend
modes. A slave processor in a multiprocessor system does not have the pull-up or
pull-down. A master processor (or ID = 0 in a single processor system) has a pull-up
before granting the bus to the host, except when the SDRAM is put in self refresh
mode. In self refresh mode, the master has a pull-down before granting the bus to
the host.
SDWE
I/O/T
(pu_0)
nc
SDRAM Write Enable. When sampled low while CAS is active, SDWE indicates an
SDRAM write access. When sampled high while CAS is active, SDWE indicates an
SDRAM read access. In other SDRAM accesses, SDWE defines the type of operation
to execute according to SDRAM specification.
Table 9. Pin Definitions—JTAG Port
Signal
Type
Term
Description
EMU
O/OD
nc1
Emulation. Connected to the processor’s JTAG emulator target board connector
only.
TCK
I
epd or epu1
Test Clock (JTAG). Provides an asynchronous clock for JTAG scan.
TDI
I
(pu_ad)
Test Data Input (JTAG). A serial data input of the scan path.
TDO
O/T
Test Data Output (JTAG). A serial data output of the scan path.
TMS
I
(pu_ad)
Test Mode Select (JTAG). Used to control the test state machine.
TRST
I/A
(pu_ad)
na
Test Reset (JTAG). Resets the test state machine. TRST must be asserted or pulsed
low after power-up for proper device operation. For more information, see Reset
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on processor ID = 0; pu_0 = internal pull-up 5 kΩ on processor ID = 0;
pu_od_0 = internal pull-up 500 Ω on processor ID = 0; pd_m = internal pull-down 5 kΩ on processor bus master; pu_m = internal pull-up
5 kΩ on processor bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up
approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect
directly to VSS
1 See the reference on Page 10 to the JTAG emulation technical reference EE-68.
Table 8. Pin Definitions—External Port SDRAM Controller (Continued)
Signal
Type
Term
Description
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on processor ID = 0; pu_0 = internal pull-up 5 kΩ on processor ID = 0;
pu_od_0 = internal pull-up 500 Ω on processor ID = 0; pd_m = internal pull-down 5 kΩ on processor bus master; pu_m = internal pull-up
5 kΩ on processor bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up
approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect
directly to VSS
相关PDF资料 |
PDF描述 |
|---|---|
| ADUC7021BCPZ62-RL7 | IC MCU 12BIT 1MSPS UART 40-LFCSP |
| ADUC7023BCPZ62I-R7 | IC MCU 12BIT 62KB FLASH 32LFCSP |
| ADUC7024BCPZ62 | IC MCU FLSH 62K ANLG I/O 64LFCSP |
| ADUC7032BSTZ-88 | IC MCU 96K FLASH DUAL 48LQFP |
| ADUC7032BSTZ-8V-RL | IC BATTERY SENSOR PREC 48-LQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-TS203SABP-05X | 制造商:Analog Devices 功能描述: |
| ADSP-TS203SABPZ050 | 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:TigerSHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-TS203SBBPZ050 | 制造商:Analog Devices 功能描述:DSP - Bulk |
| ADSQ-1410 | 制造商:MURATA-PS 制造商全称:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
| ADSQ-1410-C | 制造商:MURATA-PS 制造商全称:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
发布紧急采购，3分钟左右您将得到回复。