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| 型号： | ADSP-TS203SABP-050 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 47/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP FLOAT/FIXED 500MHZ 576BGA |
| 标准包装： | 1 |
| 系列： | TigerSHARC® |
| 类型： | 定点/浮点 |
| 接口： | 主机接口，连接端口，多处理器 |
| 时钟速率： | 500MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 512kB |
| 电压 - 输入/输出： | 2.50V |
| 电压 - 核心： | 1.05V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 576-BBGA 裸露焊盘 |
| 供应商设备封装： | 576-BGA-ED（25x25） |
| 包装： | 托盘 |
| 其它名称： | ADSP-TS203SABP050 ADSP-TS203SABP050-ND |
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Rev. D
|
Page 8 of 48
|
May 2012
from a receive register, or the DMA controller can perform
DMA transfers through four (two transmit and two receive)
dedicated link port DMA channels.
Each link port direction has three signals that control its opera-
tion. For the transmitter, LxCLKOUT is the output transmit
clock, LxACKI is the handshake input to control the data flow,
and the LxBCMPO output indicates that the block transfer is
complete. For the receiver, LxCLKIN is the input receive clock,
LxACKO is the handshake output to control the data flow, and
the LxBCMPI input indicates that the block transfer is com-
plete. The LxDATO3–0 pins are the data output bus for the
transmitter, and the LxDATI3–0 pins are the input data bus for
the receiver.
Applications can program separate error detection mechanisms
for transmit and receive operations (applications can use the
checksum mechanism to implement consecutive link port
transfers), the size of data packets, and the speed at which bytes
are transmitted.
TIMER AND GENERAL-PURPOSE I/O
The ADSP-TS203S processor has a timer pin (TMR0E) that
generates output when a programmed timer counter has
expired, and four programmable general-purpose I/O pins
(FLAG3–0) that can function as either single-bit input or out-
put. As outputs, these pins can signal peripheral devices; as
inputs, they can provide the test for conditional branching.
RESET AND BOOTING
The processor has three levels of reset:
Power-up reset – after power-up of the system (SCLK, all
static inputs, and strap pins are stable), the RST_IN pin
must be asserted (low).
Normal reset – for any chip reset following the power-up
reset, the RST_IN pin must be asserted (low).
Processor-core reset – when setting the SWRST bit in
EMUCTL, the processor core is reset, but not the external
port or I/O.
For normal operations, tie the RST_OUT pin to the
POR_IN pin.
After reset, the processor has four boot options for beginning
operation:
Boot from EPROM.
Boot by an external master (host or another ADSP-TS203S
processor).
Boot by link port.
No boot—start running from memory address selected
with one of the IRQ3–0 interrupt signals. See Table 2.
Using the this option, the processor must start running
from memory when one of the interrupts is asserted.
The processor core always exits from reset in the idle state and
waits for an interrupt. Some of the interrupts in the interrupt
vector table are initialized and enabled after reset.
For more information on boot options, see the EE-200:
ADSP-TS20x TigerSHARC Processor Boot Loader Kernels Oper-
ation on the Analog Devices website (www.analog.com)
CLOCK DOMAINS
The processor uses calculated ratios of the SCLK clock to oper-
ate, as shown in Figure 3. The instruction execution rate is equal
to CCLK. A PLL from SCLK generates CCLK which is phase-
locked. The SCLKRATx pins define the clock multiplication of
SCLK to CCLK (see Table 4 on Page 11). The link port clock is
generated from CCLK via a software programmable divisor, and
the SOC bus operates at 1/2 CCLK. Memory transfers to exter-
nal and link port buffers operate at the SOCCLK rate. SCLK also
provides clock input for the external bus interface and defines
the ac specification reference for the external bus signals. The
external bus interface runs at the SCLK frequency. The maxi-
mum SCLK frequency is one quarter the internal processor
clock (CCLK) frequency.
FILTERING REFERENCE VOLTAGE AND CLOCKS
and SCLK_VREF. These circuits provide the reference voltages
for the switching voltage reference and system clock reference.
Table 2. No Boot, Run from Memory Addresses
Interrupt
Address
IRQ0
0x3000 0000 (External Memory)
IRQ1
0x3800 0000 (External Memory)
IRQ2
0x8000 0000 (External Memory)
IRQ3
0x0000 0000 (Internal Memory)
Figure 3. Clock Domains
Figure 4. VREF Filtering Scheme
SCLKRATx
SCLK
SPD BITS,
LCTLx REGISTER
PLL
/2
/CR
CCLK
(INSTRUCTION RATE)
SOCCLK
(PERIPHERAL BUS RATE)
LxCLKOUT
(LINK OUTPUT RATE)
EXTERNAL INTERFACE
VDD_IO
VSS
VREF
R1
R2
C1
C2
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-TS203SABP-05X | 制造商:Analog Devices 功能描述: |
| ADSP-TS203SABPZ050 | 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:TigerSHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-TS203SBBPZ050 | 制造商:Analog Devices 功能描述:DSP - Bulk |
| ADSQ-1410 | 制造商:MURATA-PS 制造商全称:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
| ADSQ-1410-C | 制造商:MURATA-PS 制造商全称:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
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