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| 型号： | ADUC7129BSTZ126-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 37/92页 |
| 文件大小： | 0K |
| 描述： | IC DAS MCU ARM7 ADC/DDS 80-LQFP |
| 产品培训模块： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters Process Control Direct Digital Synthesis Tutorial Series (1 of 7): Introduction |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外围设备： | PLA，POR，PWM，PSM，温度传感器，WDT |
| 输入/输出数： | 38 |
| 程序存储器容量： | 126KB（63K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 8K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 10x12b; D/A 1x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 80-LQFP |
| 包装： | 标准包装 |
| 其它名称： | ADUC7129BSTZ126-RLDKR |
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ADuC7128/ADuC7129
Rev. 0 | Page 42 of 92
Table 41. FEExSTA MMR Bit Designations
Bit
Description
15:6
Reserved.
5
Reserved.
4
Reserved.
3
Flash/EE Interrupt Status Bit.
Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the
FEExMOD register is set.
Cleared when reading FEExSTA register.
2
Flash/EE Controller Busy.
Set automatically when the controller is busy.
Cleared automatically when the controller is not busy.
1
Command Fail.
Set automatically when a command completes unsuccessfully.
Cleared automatically when reading FEExSTA register.
0
Command Complete.
Set by MicroConverter when a command is complete.
Cleared automatically when reading FEExSTA register.
Table 42. FEExMOD MMR Bit Designations
Bit
Description
7:5
Reserved.
4
Flash/EE Interrupt Enable.
Set by user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete.
Cleared by user to disable the Flash/EE interrupt
3
Erase/Write Command Protection.
Set by user to enable the erase and write commands.
Cleared to protect the Flash/EE memory against erase/write command.
2
Reserved. Should always be set to 0 by the user.
1:0
Flash/EE Wait States. Both Flash/EE blocks must have the same wait state value for any change to take effect.
Table 43. Command Codes in FEExCON
Code
Command
Description
Null
Idle State.
Single read
Load FEExDAT with the 16-bit data indexed by FEExADR.
Single write
Write FEExDAT at the address pointed by FEExADR. This operation takes 50 μs.
Erase/Write
Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation
takes 20 ms.
Single verify
Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the comparison
is returned in FEExSTA Bit 1.
Single erase
Erase the page indexed by FEExADR.
Mass erase
Erase user space. The 2 kB of kernel are protected in Block 0. This operation takes 2.48 sec. To prevent accidental
execution, a command sequence is required to execute this instruction.
0x07
Reserved
Reserved.
0x08
Reserved
Reserved.
0x09
Reserved
Reserved.
0x0A
Reserved
Reserved.
0x0B
Signature
Gives a signature of the 64 kB of Flash/EE in the 24-bit FEExSIGN MMR. This operation takes 32,778 clock cycles.
0x0C
Protect
This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase
(0x06) or with the key.
0x0D
Reserved
Reserved.
0x0E
Reserved
Reserved.
0x0F
Ping
No Operation, Interrupt Generated.
1 The FEExCON register always reads 0x07 immediately after execution of any of these commands.
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