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参数资料
| 型号： | ADUC7129BSTZ126-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 70/92页 |
| 文件大小： | 0K |
| 描述： | IC DAS MCU ARM7 ADC/DDS 80-LQFP |
| 产品培训模块： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters Process Control Direct Digital Synthesis Tutorial Series (1 of 7): Introduction |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外围设备： | PLA，POR，PWM，PSM，温度传感器，WDT |
| 输入/输出数： | 38 |
| 程序存储器容量： | 126KB（63K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 8K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 10x12b; D/A 1x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 80-LQFP |
| 包装： | 标准包装 |
| 其它名称： | ADUC7129BSTZ126-RLDKR |
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ADuC7128/ADuC7129
Rev. 0 | Page 72 of 92
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 30 interrupt sources on the ADuC7128/ADuC7129
controlled by the interrupt controller. Most interrupts are generated
from the on-chip peripherals, such as ADC and UART. Two
additional interrupt sources are generated from external interrupt
request pins, XIRQ0 and XIRQ1. The ARM7TDMI CPU core
only recognizes interrupts as one of two types: a normal interrupt
request (IRQ) or a fast interrupt request (FIQ). All the interrupts
can be masked separately.
The control and configuration of the interrupt system are managed
through nine interrupt-related registers, four dedicated to IRQ,
four dedicated to FIQ, and an additional MMR that is used to
select the programmed interrupt source. The bits in each IRQ
and FIQ register represent the same interrupt source as described
in Table 104.
Table 104. IRQ/FIQ MMRs Bit Designations
Bit
Description
0
FIQ Source.
1
SWI. Not used in IRQEN/CLR and FIQEN/CLR.
2
Timer0.
3
Timer1.
4
Wake-Up Timer—Timer2.
5
Watchdog Timer—Timer3.
6
Timer4.
7
Flash Controller 0.
8
Flash Controller 1.
9
ADC.
10
Quadrature Encoder.
11
I2C0 Slave.
12
I2C1 Slave.
13
I2C0 Master.
14
I2C1 Master.
15
SPI Slave.
16
SPI Master.
17
UART0.
18
UART1.
19
External IRQ0.
20
Comparator.
21
PSM.
22
External IRQ1.
23
PLA IRQ0.
24
PLA IRQ1.
25
External IRQ2.
26
External IRQ3.
27
PWM Trip.
28
PLL Lock.
29
Reserved.
30
Reserved.
IRQ
The interrupt request (IRQ) is the exception signal to enter the
IRQ mode of the processor. It is used to service general-
purpose interrupt handling of internal and external events.
The four 32-bit registers dedicated to IRQ are listed in Table 105.
Table 105. IRQ Interface MMRs
Register
Description
IRQSIG
Reflects the status of the different IRQ sources.
If a peripheral generates an IRQ signal, the
corresponding bit in the IRQSIG is set; otherwise,
it is cleared. The IRQSIG bits are cleared when the
interrupt in the particular peripheral is cleared. All
IRQ sources can be masked in the IRQEN MMR.
IRQSIG is read only.
IRQEN
Provides the value of the current enable mask. When
set to 1, the source request is enabled to create an
IRQ exception. When set to 0, the source request is
disabled or masked but does not create an IRQ
exception. To clear a bit in IRQEN, use the IRQCLR MMR.
IRQCLR
Write-only register allows clearing the IRQEN register
to mask an interrupt source. Each bit set to 1 clears
the corresponding bit in the IRQEN register without
affecting the remaining bits. The pair of registers,
IRQEN and IRQCLR, allows independent manipulation
of the enable mask without requiring an automatic
read-modify-write.
IRQSTA
Read-only register provides the current enabled IRQ
source status. When set to 1, that source should
generate an active IRQ request to the ARM7TDMI
core. There is no priority encoder or interrupt vector
generation. This function is implemented in software
in a common interrupt handler routine. All 32 bits are
logically OR’ed to create the IRQ signal to the
ARM7TDMI core.
FIQ
The fast interrupt request (FIQ) is the exception signal to enter
the FIQ mode of the processor. It is provided to service data
transfer or communication channel tasks with low latency. The
FIQ interface is identical to the IRQ interface providing the
second level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.
Bit 31 to Bit 1 of FIQSTA are logically OR’ed to create the FIQ
signal to the core and Bit 0 of both the FIQ and IRQ registers
(FIQ source).
The logic for FIQEN and FIQCLR does not allow an interrupt
source to be enabled in both IRQ and FIQ masks. A bit set
to 1 in FIQEN, as a side effect, clears the same bit in IRQEN.
A bit set to 1 in IRQEN, as a side effect, clears the same bit
in FIQEN. An interrupt source can be disabled in both IRQEN and
FIQEN masks.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADUC7129BSTZ126-RL2 | 制造商:AD 制造商全称:Analog Devices 功能描述:Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC |
| aduc7229bcpz126 | 制造商:Analog Devices 功能描述: |
| ADUC7229BCPZ126-RL | 制造商:Analog Devices 功能描述: |
| ADUC812 | 制造商:AD 制造商全称:Analog Devices 功能描述:MicroConverter⑩, Multichannel 12-Bit ADC with Embedded FLASH MCU |
| ADUC812_03 | 制造商:AD 制造商全称:Analog Devices 功能描述:MicroConverter㈢, Multichannel 12-Bit ADC with Embedded Flash MCU |
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