- 您现在的位置：买卖IC网 > PDF目录11791 > ADUC7129BSTZ126-RL (Analog Devices Inc)IC DAS MCU ARM7 ADC/DDS 80-LQFP PDF资料下载
参数资料
| 型号： | ADUC7129BSTZ126-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 64/92页 |
| 文件大小： | 0K |
| 描述： | IC DAS MCU ARM7 ADC/DDS 80-LQFP |
| 产品培训模块： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters Process Control Direct Digital Synthesis Tutorial Series (1 of 7): Introduction |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外围设备： | PLA，POR，PWM，PSM，温度传感器，WDT |
| 输入/输出数： | 38 |
| 程序存储器容量： | 126KB（63K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 8K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 10x12b; D/A 1x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 80-LQFP |
| 包装： | 标准包装 |
| 其它名称： | ADUC7129BSTZ126-RLDKR |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页当前第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页
Rev. 0 | Page 67 of 92
I2CxSRX Register
Name
Address
Default Value
Access
I2C0SRX
0xFFFF0808
0x00
R
I2C1SRX
0xFFFF0908
0x00
R
I2CxSRX is a receive register for the slave channel.
I2CxSTX Register
Name
Address
Default Value
Access
I2C0STX
0xFFFF080C
0x00
W
I2C1STX
0xFFFF090C
0x00
W
I2CxSTX is a transmit register for the slave channel.
I2CxMRX Register
Name
Address
Default Value
Access
I2C0MRX
0xFFFF0810
0x00
R
I2C1MRX
0xFFFF0910
0x00
R
I2CxMRX is a receive register for the master channel.
I2CxMTX Register
Name
Address
Default Value
Access
I2C0MTX
0xFFFF0814
0x00
W
I2C1MTX
0xFFFF0914
0x00
W
I2CxMTX is a transmit register for the master channel.
I2CxCNT Register
Name
Address
Default Value
Access
I2C0CNT
0xFFFF0818
0x00
R/W
I2C1CNT
0xFFFF0918
0x00
R/W
I2CxCNT is a master receive data count register. If a master read
transfer sequence is initiated, the I2CxCNT register denotes the
number of bytes (1) to be read from the slave device. By default
this counter is 0, which corresponds to the expected one byte.
I2CxADR Register
Name
Address
Default Value
Access
I2C0ADR
0xFFFF081C
0x00
R/W
I2C1ADR
0xFFFF091C
0x00
R/W
I2CxADR is a master address byte register. The I2CxADR value
is the device address that the master wants to communicate
with. It is automatically transmitted at the start of a master
transfer sequence if there is no valid data in the I2CxMTX
register when the master enable bit is set.
I2CxBYT Register
Name
Address
Default Value
Access
I2C0BYT
0xFFFF0824
0x00
R/W
I2C1BYT
0xFFFF0924
0x00
R/W
I2CxBYT is a broadcast byte register.
I2CxALT Register
Name
Address
Default Value
Access
I2C0ALT
0xFFFF0828
0x00
R/W
I2C1ALT
0xFFFF0928
0x00
R/W
I2CxALT is a hardware general call ID register used in slave mode.
I2CxCFG Register
Name
Address
Default Value
Access
I2C0CFG
0xFFFF082C
0x00
R/W
I2C1CFG
0xFFFF092C
0x00
R/W
I2CxCFG is a configuration register.
Table 94. I2C0CFG MMR Bit Designations
Bit
Description
31:15
Reserved. These bits should be written by the user as 0.
14
Enable Stop Interrupt.
Set by user to generate an interrupt upon receiving a stop condition and after receiving a valid start condition and matching
address.
Cleared by user to disable the generation of an interrupt upon receiving a stop condition.
13
Reserved. This bit should be written by the user as 0.
12
Reserved. This bit should be written by the user as 0.
11
Enable Stretch SCL. Holds SCL low.
Set by user to stretch the SCL line.
Cleared by user to disable stretching of the SCL line.
10
Reserved. This bit should be written by the user as 0.
9
Slave Tx FIFO Request Interrupt Enable.
Cleared by user to generate an interrupt request just after the negative edge of the clock for the R/W bit. This allows the user to
input data into the slave Tx FIFO if it is empty. At 400 kSPS, and with the core clock running at 41.78 MHz, the user has 45 clock
cycles to take appropriate action, taking interrupt latency into account.
Set by user to disable the slave Tx FIFO request interrupt.
8
General Call Status Bit Clear.
Set by user to clear the general call status bits.
Cleared automatically by hardware after the general call status bits have been cleared.
相关PDF资料 |
PDF描述 |
|---|---|
| D38999/20FC8SC | CONN RCPT 8POS WALL MNT W/SCKT |
| D38999/26WC8PB | CONN PLUG 8POS STRAIGHT W/PINS |
| MS27473E18A11P | CONN PLUG 11POS STRAIGHT W/PINS |
| AT32UC3C2512C-Z2ZR | IC MCU AVR32 512K FLASH 64QFN |
| MS27484E10B98P | CONN PLUG 6POS STRAIGHT W/PINS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADUC7129BSTZ126-RL2 | 制造商:AD 制造商全称:Analog Devices 功能描述:Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC |
| aduc7229bcpz126 | 制造商:Analog Devices 功能描述: |
| ADUC7229BCPZ126-RL | 制造商:Analog Devices 功能描述: |
| ADUC812 | 制造商:AD 制造商全称:Analog Devices 功能描述:MicroConverter⑩, Multichannel 12-Bit ADC with Embedded FLASH MCU |
| ADUC812_03 | 制造商:AD 制造商全称:Analog Devices 功能描述:MicroConverter㈢, Multichannel 12-Bit ADC with Embedded Flash MCU |
发布紧急采购，3分钟左右您将得到回复。