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参数资料
| 型号： | ADUC7129BSTZ126-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 48/92页 |
| 文件大小： | 0K |
| 描述： | IC DAS MCU ARM7 ADC/DDS 80-LQFP |
| 产品培训模块： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters Process Control Direct Digital Synthesis Tutorial Series (1 of 7): Introduction |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外围设备： | PLA，POR，PWM，PSM，温度传感器，WDT |
| 输入/输出数： | 38 |
| 程序存储器容量： | 126KB（63K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 8K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 10x12b; D/A 1x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 80-LQFP |
| 包装： | 标准包装 |
| 其它名称： | ADUC7129BSTZ126-RLDKR |
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ADuC7128/ADuC7129
Rev. 0 | Page 52 of 92
Bit
Name
Description
2.
4.
8.
16.
32.
64.
128.
6
PWMCP0
256.
5
POINV
Set to 1 by the user to invert all PWM outputs.
Cleared by user to use PWM outputs as normal.
4
HOFF
High Side Off.
Set to 1 by the user to force PWM1 and PWM3 outputs high. This also forces PWM2 and PWM4 low.
Cleared by user to use the PWM outputs as normal.
3
LCOMP
Load Compare Registers.
Set to 1 by the user to load the internal compare registers with the values in PWMxCOMx on the next transition of the
PWM timer from 0x00 to 0x01.
Cleared by user to use the values previously stored in the internal compare registers.
2
DIR
Direction Control.
Set to 1 by the user to enable PWM1 and PWM2 as the output signals while PWM3 and PWM4 are held low.
Cleared by user to enable PWM3 and PWM4 as the output signals while PWM1 and PWM2 are held low.
1
HMODE
Enables H-bridge mode.
Set to 1 by the user to enable H-Bridge mode and Bit 1 to Bit 5 of PWMCON1.
Cleared by user to operate the PWMs in standard mode.
0
PWMEN
Set to 1 by the user to enable all PWM outputs.
Cleared by user to disable all PWM outputs.
In H-bridge mode, HMODE = 1. See Table 65 to determine the PWM outputs.
Table 65. PWM Output Selection
PWMCOM1 MMR
PWM Outputs
ENA
HOFF
POINV
DIR
PWM1
PWM2
PWMR3
PWM4
0
x
1
x
1
x
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1 HS = high side, LS = low side.
On power-up, PWMCON1 defaults to 0x12 (HOFF = 1 and
HMODE = 1). All GPIO pins associated with the PWM are
configured in PWM mode by default (see Table 66).
Table 66. Compare Register
Name
Address
Default Value
Access
PWM1COM1
0xFFFF0F84
0x00
R/W
PWM1COM2
0xFFFF0F88
0x00
R/W
PWM1COM3
0xFFFF0F8C
0x00
R/W
PWM2COM1
0xFFFF0F94
0x00
R/W
PWM2COM2
0xFFFF0F98
0x00
R/W
PWM2COM3
0xFFFF0F9C
0x00
R/W
PWM3COM1
0xFFFF0FA4
0x00
R/W
PWM3COM2
0xFFFF0FA8
0x00
R/W
PWM3COM3
0xFFFF0FAC
0x00
R/W
The PWM trip interrupt can be cleared by writing any value to
the PWMICLR MMR. Note that when using the PWM trip
interrupt, the PWM interrupt should be cleared before exiting
the ISR. This prevents generation of multiple interrupts.
PWM CONVERT START CONTROL
The PWM can be configured to generate an ADC convert start
signal after the active low side signal goes high. There is a program-
mable delay between when the low-side signal goes high and
the convert start signal is generated.
This is controlled via the PWMCON2 MMR. If the delay
selected is higher than the width of the PWM pulse, the
interrupt remains low.
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