CLKINP
CLKINN
Clock
Divider
%1,2,4
Clock
Divider
%1,2,4
PLL
X2,4
ADC_CLK
DAC_CLK
MUX
PLL_ENABLE
REG_SE_CLK
DIV_ADC<1:0>
DIV_DAC<1:0>
DCC
(Duty Cycle
Correction)
MUX
ENABLE_DCC
Single-
ended
Buffer
Single-
ended
Buffer
Differential
Buffer
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
Figure 10-20. Block Diagram of Clocking Path
Three cases are considered:
Case 1: DAC_CLK and ADC_CLK are at same rate: In this case, either CLKINP and CLKINN should be
driven by a differential clock (common to both the ADC and DAC) or two single ended clocks, both at the
same rate.
Case 2: DAC_CLK and ADC_CLK are at different rates such that the higher rate is 2X or 4X of the
lower rate: In this case, we again recommend driving CLKINP/CLKINN differentially (or by two equal rate
single ended clocks) at the higher of two rates and dividng internally by the factor of 2 (or 4) on the
channel that requires the lower rate clock.
Case 3: DAC_CLK and ADC_CLK are at different rates with the DAC_CLK being at 8X or 16X of the
ADC_CLK: In this case, we recommend driving CLKINP/CLKINN differentially (or by two equal rate single
ended clocks) at 4X of ADC_CLK rate, dividing it by 4 for the ADC, and multiplying it by 2 (or 4) for the
DAC.
Case 4: DAC_CLK and ADC_CLK are at different rates that are harmonically related but not at rates
covered by Case 2 or Case 3: In this case, there is no alternative but to drive CLKINP and CLKINN with
two different rate clocks. If phase control of the two clocks is possible, we recommend that the phases be
adjusted such that the two clocks have rise/fall edges that do not come within 5 ns of each other. We also
recommend that the driving clock rates be as close to each other as possible.
Case 5: DAC_CLK and ADC_CLK are at different rates that are non-harmonically related: This is the
worst case and it is recommended to avoid operating the AFE in full duplex mode with such clock rates.
The presence of non-harmonically related clocks at two adjacent pins can cause periodic modulation in
the sampling instant that can result in huge spurs that get worse at higher ADC input frequencies (and
DAC output frequencies). At 70 MHz IF, these spur levels could be as large as –45 dBc.
10.12 Half Duplex Operation – Coupling Considerations
If the ADC and DAC are driven externally by unequal rate clocks, then ensure that these clocks are not on
simultaneously. For example, in half duplex mode with the Tx active, ensure that the ADC clock to the
device is shut off. If the ADC and DAC are driven by equal rate clocks, then it is not required to shut off
the ADC clock when the Tx is active (and DAC clock when the Rx is active).
10.13 Half Duplex Operation Through a Common I/O Interface
If the AFE7222/7225 is to be always operated in Half Duplex mode through a common I/O interface for the
RX and TX (to reuse the same bus), then the RX and TX data and clocks can be tied on the board as
illustrated below:
Copyright 2011–2012, Texas Instruments Incorporated
DIGITAL INTERFACE
93