参数资料
| 型号： | AFE7222IRGCT |
| 厂商： | Texas Instruments |
| 文件页数： | 36/106页 |
| 文件大小： | 0K |
| 描述： | IC AFE 12BIT 65/130MSPS 64VQFN |
| 标准包装： | 1 |
| 位数： | 12 |
| 通道数： | 4 |
| 功率（瓦特）： | 610mW |
| 电压 - 电源，模拟： | 2.85 V ~ 3.6 V |
| 电压 - 电源，数字： | 1.7 V ~ 1.9 V |
| 封装/外壳： | 64-VFQFN 裸露焊盘 |
| 供应商设备封装： | 64-VQFN 裸露焊盘（9x9） |
| 包装： | 标准包装 |
| 其它名称： | 296-30113-6 |
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SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
RX_CMIX_PHASE_INCR – This bit can be used to control the mixing phase without the need for the
SYNC pin. A 0 to 1 transition on this bit causes the phase of mixing in the RX CMIX to be incremented by
1 with respect to the current phase of mixing . To increment the phase of mixing more than once, clear
and then set this bit once again. Syncing needs to be disabled for RX CMIX for this mode to work. (This
means that both global syncing, as well as block level syncing needs to be disabled for CMIX )
RX_CMIX_PHASE(1:0) – The value programmed into this is applied as the RX CMIX phase, when the
CMIX is synced, Syncing needs to be enabled for CMIX for this mode to work.
RX_DIV_PHASE – The value programmed into this is applied as the RX Divider phase, when the divider
is synced. If divider is not synced, then output latency can differ by 1 with respect to the sampling clock.
The RX divider is used whenever the decimation filter is enabled.
RX_DIV_PHASE_INV – This bit is used to control the phase of the RX divider without the need for the
SYNC pin. A 0 to 1 transition on this bit causes the phase of division in the RX Divider to be inverted by 1
with respect to the current phase of division. To invert the phase of division more than once, clear and
then set this bit once again. Syncing needs to be disabled for RX Divider for this mode to work.
Register Name – CONFIG63 – Address 0x167, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
RX_BYP_SRC
RX_BYP
RX_CHB_PDN_SRC
RX_CHB_PDN
RX_CHA_PDN
RX_CHA_PDN_S
RX_DIS
RC
RX_DIS – Disables the RX signal chain of both channels. All blocks in the signal chain are powered down,
and the RX output is mid-code.
RX_CHA_PDN_SRC – Setting this causes the value programmed into RX_CHA_PDN to take effect.
RX_CHA_PDN – Powers down Channel A in Rx signal chain. Output of the channel is mid code. Set
RX_CHA_PDN_SRC for this to take effect. Output clock is not powered down.
RX_CHB_PDN – Powers down Channel B in Rx signal chain. Output of the channel is mid code. Set
RX_CHB_PDN_SRC for this to take effect. Output clock is not powered down.
RX_CHB_PDN_SRC – Setting this causes the value programmed into RX_CHB_PDN to take effect.
Note that when in default mode of operation (none of the register-selectable digital features enabled), all 4
of above bits (RX_CHA_PDN, RX_CHA_PDN_SRC, RX_CHB_PDN, RX_CHB_PDN_SRC) have to be set
together to ‘1’ for them to take effect. However, if any of the digital features (like interpolation, Fine mixer,
Coarse mixer, or QMC gain/phase or offset) are enabled, then the channel A can be independently
powered down using bits RX_CHA_PDN and RX_CHA_PDN_SRC, and channel B can be independently
powered down using bits RX_CHB_PDN and RX_CHB_PDN_SRC.
RX_BYP – The inputs to both the Rx channels are directly passed to the outputs. Set RX_BYP_SRC for
this to take effect. Use this mode to operate the Rx with lowest latency.
RX_BYP_SRC – Setting this causes the value programmed into RX_BYP to take effect.
Register Name – CONFIG64 – Address 0x168, Default = 0x00
<7> <6> <5>
<4>
<3>
<2>
<1>
<0>
RX_GLOBAL_SYNC_
RX_QMC_GAIN_PH_SYNC_
RX_QMC_OFF_SYNC_
RX_DIV_SYNC_
RX_CMIX_SYNC_
DIS
RX_CMIX_SYNC_DIS – Disables Syncing of the Rx Coarse mixer. This takes effect only when
RX_GLOBAL_SYNC_DIS is set.
RX_DIV_SYNC_DIS – Disables Syncing of the Rx clock divider .This takes effect only when
RX_GLOBAL_SYNC_DIS is set.
RX_QMC_OFF_SYNC_DIS – Disables Syncing of Rx QMC Offset Correction .This takes effect only when
RX_GLOBAL_SYNC_DIS is set.
Copyright 2011–2012, Texas Instruments Incorporated
REGISTER DESCRIPTIONS
35
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