参数资料
| 型号： | AFE7222IRGCT |
| 厂商： | Texas Instruments |
| 文件页数： | 89/106页 |
| 文件大小： | 0K |
| 描述： | IC AFE 12BIT 65/130MSPS 64VQFN |
| 标准包装： | 1 |
| 位数： | 12 |
| 通道数： | 4 |
| 功率（瓦特）： | 610mW |
| 电压 - 电源，模拟： | 2.85 V ~ 3.6 V |
| 电压 - 电源，数字： | 1.7 V ~ 1.9 V |
| 封装/外壳： | 64-VFQFN 裸露焊盘 |
| 供应商设备封装： | 64-VQFN 裸露焊盘（9x9） |
| 包装： | 标准包装 |
| 其它名称： | 296-30113-6 |
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DAC_DCLKIN
DACDATA <11:0>
A
B
A
B
A
B
DAC_DCLKIN
DACDATA <11:0>
A
B
A
th
tsu
th
tsu
tCLK
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
10.3 PARALLEL CMOS DAC TX DATA
The 12-bit DAC-A and DAC-B data is interleaved (A then B) into one 12-bit word on pins
DACDATA0:DACDATA11 at twice the rate of each pattern with a DDR clock (data transitions on rising
and falling edges). This can be quadrature data or two independent transmit channels.
Figure 10-3. TX CMOS Interleaved Input
10.4 TIMING INFORMATION FOR PARALLEL CMOS DAC TX DATA
tCLK = Time period of DAC input data clock (same as time period of DAC output clock when interpolation is set to 1).
Figure 10-4. TX CMOS Input Timing
10.5 LOW POWER RX CMOS MODE
The default RX CMOS mode uses an internal PLL to position the clock edges in the middle of the data
window. While operating at speeds lower than 40 MSPS, a low power CMOS mode can be enabled (set
bit MODE_LP_CMOS to 1). In this mode, the PLL is bypassed and the clock edges are set relative to the
data transitions through delay elements. Bypassing the PLL saves about 20 mW of power. However,
because the delay elements operate in open loop, there is no tight control on the precise delay and there
can be a chip to chip variation. At low speeds, there will be sufficient set up and hold time inspite of the
variations in the clock edge relative to the data. An advantage of the low power RX CMOS mode is that
the recovery of the RX from powerdown is much faster because of the absence of the PLL. For example,
with the low power RX CMOS mode enabled, the RX recovers from a state of OFF clock to a state of ON
clock in 5 us (as compared to 20 us when in default RX CMOS mode). Another advantage of this low
power RX CMOS mode is that the minimum frequency of operation is extended down to 2.5 MSPS (from
10 MSPS).
10.6 SERIAL LVDS DAC TX INTERFACE
12-bit DAC input data is serialized onto one or two LVDS pairs per DAC. DACA and DACB data inputs
can be quadrature data or two independent receive channels. Two serialization modes are available.
1-Wire mode: 1 LVDS pair for the data to each DAC. It will operate in a DDR fashion serialized to a
frequency of 6x the pattern word rate. A frame clock (DAC_FCLKINP/N) at the word rate and a bit
clock (DAC_DCLKINP/N) at 6x. Example: 50MSPS 12-bit pattern will serialize to 300MHz on each
LVDS pair, frame clock of 50MHz and bit clock of 300MHz. Effective serial data rate is 600Mbps due to
bit transitions on rising and falling edge of bit clock. Recommended maximum word rate is ~65MSPS in
this mode.
Copyright 2011–2012, Texas Instruments Incorporated
DIGITAL INTERFACE
83
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| AFE7225 | 制造商:TI 制造商全称:Texas Instruments 功能描述:Analog Front End Wideband Mixed-Signal Transceiver |
| AFE7225EVM | 功能描述:射频开发工具 AFE7225 Eval Mod RoHS:否 制造商:Taiyo Yuden 产品:Wireless Modules 类型:Wireless Audio 工具用于评估:WYSAAVDX7 频率: 工作电源电压:3.4 V to 5.5 V |
| AFE7225IRGC25 | 功能描述:射频前端 Dual 12B,125MSPS ADC RoHS:否 制造商:Skyworks Solutions, Inc. 类型: 工作频率:2.4 GHz, 5 GHz 最大数据速率:54 Mbps 噪声系数: 工作电源电压:3.3 V 电源电流:180 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-32 |
| AFE7225IRGCR | 功能描述:射频前端 Dual 12B,125MSPS ADC RoHS:否 制造商:Skyworks Solutions, Inc. 类型: 工作频率:2.4 GHz, 5 GHz 最大数据速率:54 Mbps 噪声系数: 工作电源电压:3.3 V 电源电流:180 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-32 |
| AFE7225IRGCT | 功能描述:射频前端 Dual 12B,125MSPS ADC RoHS:否 制造商:Skyworks Solutions, Inc. 类型: 工作频率:2.4 GHz, 5 GHz 最大数据速率:54 Mbps 噪声系数: 工作电源电压:3.3 V 电源电流:180 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-32 |
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