参数资料
| 型号： | AFE7222IRGCT |
| 厂商： | Texas Instruments |
| 文件页数： | 15/106页 |
| 文件大小： | 0K |
| 描述： | IC AFE 12BIT 65/130MSPS 64VQFN |
| 标准包装： | 1 |
| 位数： | 12 |
| 通道数： | 4 |
| 功率（瓦特）： | 610mW |
| 电压 - 电源，模拟： | 2.85 V ~ 3.6 V |
| 电压 - 电源，数字： | 1.7 V ~ 1.9 V |
| 封装/外壳： | 64-VFQFN 裸露焊盘 |
| 供应商设备封装： | 64-VQFN 裸露焊盘（9x9） |
| 包装： | 标准包装 |
| 其它名称： | 296-30113-6 |
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SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
Typical values are at 25°C, AVDD3_DAC = 3.0 V, AVDD3_AUX = 3.0 V, AVDD18_ADC = 1.8 V, DVDD18_CLK = 1.8 V,
DVDD18_DAC = 1.8 V, DVDD18 = 1.8 V, sampling frequency = 125 MSPS, sine wave input clock, 1.5 Vpp clock amplitude,
CLOAD = 5 pF
(1), R
LOAD = 100 Ω
(2), unless otherwise noted. Min and max values are across the full temperature range T
MIN = -
40°C to TMAX = 85°C, AVDD3_DAC = 3.0 V, AVDD3_AUX = 3.0 V, AVDD18_ADC = 1.8 V, DVDD18_CLK = 1.8 V,
DVDD18_DAC = 1.8 V, DVDD18 = 1.7 V to 1.9 V
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
th
Data hold time (5)
Zero-crossing of CLKOUTP to data becoming invalid (5)
0.26
0.4
ns
Input clock rising edge cross-over to output clock rising edge
tPDI
Clock propagation delay
cross-over 10 MSPS
≤ Sampling frequency ≤ 65 MSPS Ts =
tPDI = 0.5*Ts + tDELAY
ns
1/Sampling frequency
tdelay
11.5
13.5
15.5
ns
Variation of tdelay
Between two devices at same temperature and DVDD18 supply
±300
ps
Duty cycle of differential clock, (CLKOUTP-CLKOUTM) 10
LVDS bit clock duty cycle
50%
MSPS
≤ Sampling frequency ≤ 65 MSPS
COMMON
Rise time measured from -100 mV to +100 mV Fall time
tRISE,
Data rise time, Data fall
measured from +100 mV to -100 mV 10 MSPS
≤ Sampling
0.08
ns
tFALL
time
frequency
≤ 125 MSPS
Rise time measured from -100 mV to +100 mV Fall time
tCLKRISE,
Output clock rise time,
measured from +100 mV to -100 mV 10 MSPS
≤ Sampling
0.1
ns
tCLKFALL
Output clock fall time
frequency
≤ 125 MSPS
CMOS OUTPUT INTERFACE (6), Sampling frequency = 105MSPS(7)
tsu
Data setup time (8)
Data valid to cross-over of ADC_DCLKOUT (8)
0.5
1.4
ns
th
Data hold time (8)
Cross-over of ADC_DCLKOUT to data becoming invalid (8)
1.4
1.8
ns
Input clock rising edge cross-over to output clock rising edge
tPDI
Clock propagation delay
cross-over 10 MSPS
≤ Sampling frequency ≤ 105 MSPS Ts =
tPDI = 0.5*Ts + tDELAY
ns
1/Sampling frequency
tdelay
14
16.5
19
ns
Variation of tdelay
Between two devices at same temperature and DVDD18 supply
±350
ps
Duty cycle of output clock, ADC_DCLKOUT 10 MSPS
≤
Output clock duty cycle
46%
Sampling frequency
≤ 105 MSPS
Rise time measured from 20% to 80% of DVDD18 Fall time
tRISE,
Data rise time, Data fall
measured from 80% to 20% of DVDD18 1
≤ Sampling
0.76
ns
tFALL
time
frequency
≤ 105 MSPS
Rise time measured from 20% to 80% of DVDD18 Fall time
tCLKRISE,
Output clock rise time,
measured from 80% to 20% of DRVDD 1
≤ Sampling frequency
0.74
ns
tCLKFALL
Output clock fall time
≤ 105 MSPS
(6)
For Fs > 105 MSPS, it is recommended to use external clock for data capture and NOT the device output clock signal
(ADC_DCLKOUT).
(7)
For Fs > 65MSPS, CMOS output buffers strength is increased by writing serial register bits STR_CTRL<1:0> = '10'.
(8)
Data valid refers to LOGIC HIGH of 1.26 V and LOGIC LOW of 0.54 V.
16
ELECTRICAL SPECIFICATIONS
Copyright 2011–2012, Texas Instruments Incorporated
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