参数资料
| 型号： | AFE7222IRGCT |
| 厂商： | Texas Instruments |
| 文件页数： | 34/106页 |
| 文件大小： | 0K |
| 描述： | IC AFE 12BIT 65/130MSPS 64VQFN |
| 标准包装： | 1 |
| 位数： | 12 |
| 通道数： | 4 |
| 功率（瓦特）： | 610mW |
| 电压 - 电源，模拟： | 2.85 V ~ 3.6 V |
| 电压 - 电源，数字： | 1.7 V ~ 1.9 V |
| 封装/外壳： | 64-VFQFN 裸露焊盘 |
| 供应商设备封装： | 64-VQFN 裸露焊盘（9x9） |
| 包装： | 标准包装 |
| 其它名称： | 296-30113-6 |
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C
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a
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M
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(C
M
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)
RX RMS /
Peak
Power Meter
Q
M
C
G
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/
P
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SYNC
/2
H
B
F
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RX Output A
(I Channel)
F
in
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M
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r
NCO
SYNC
RX Output B
(Q Channel)
RX Input A
RX Input B
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
between the read and write pointers becomes either 0,1 or 2. Detection of this collision condition
automatically causes masks the DACs to give out an output corresponding to mid code. The read and
write pointer differing by 2 is referred to as 2-way detection. 2-away detection can be prevented from
triggering collision by setting MASK_2_AWAY_DET in CONFIG 1. Collision detection is done once every
8 input samples.
EN_IP_CLK_STOP_DET – When set, the condition of input clock being stopped causes the DAC outputs
to be forced to mid code.
Register Name – CONFIG59 – Address 0x140, Default = 0x00 (Read Only)
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
FIFO_ERROR
FIFO_COLLISION
FIFO_1_AWAY
FIFO_2_AWAY
INP_CLK_STOP
These are refreshed at the rate of the divided DAC_CLK.
INP_CLK_STOP – If set, it indicates that the input clock has been detected as having been stopped.
FIFO_2_AWAY – If set, it indicates that the condition of the read and write pointers being 2 locations
away from each other has been detected.
FIFO_1_AWAY – If set, it indicates that the condition of the read and write pointers being 1 location away
from each other has been detected.
FIFO_COLLISION – If set, this indicates that the read and write pointers have been detected as
overlapping with each other
FIFO_ERROR – If set, this indicates that either Collision , or 1-away or 2-away condition has been
detected.
Register Name – CONFIG60 – Address 0x141, Default = 0x00 (Read Only)
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
FIFO_INP_PTR(2:0)
FIFO_OP_PTR(2:0)
FIFO_OP_PTR(2:0) – Containts the FIFO read pointer value. Its written into the register when
STORE_FIFO_PTRS is set in CONFIG2. It is not updated once the device is configured into readout
mode.
FIFO_INP_PTR(2:0) – Containts the FIFO write pointer value. Its written into the register when
STORE_FIFO_PTRS is set in CONFIG2. It is not updated once the device is configured into readout
mode.
5.2
RECEIVE DIGITAL SIGNAL CHAIN REGISTERS
Figure 5-3. Signal Chain
Copyright 2011–2012, Texas Instruments Incorporated
REGISTER DESCRIPTIONS
33
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