SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (November 2011) to Revision A
Page
Changed DETAILED BLOCK DIAGRAM
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Deleted product preview for AFE7225 from PACKAGE/ORDERING INFORMATION
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Changed SUPPLY CHARACTERISTICS
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Changed TX DAC ELECTRICAL CHARACTERISTICS
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Changed Data setup times
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Changed Data hold times
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Added Note to TIMING REQUIREMENTS FOR RECEIVE PATH – LVDS AND CMOS MODES
Changed tdelay times .............................................................................................................. 16
Changed Output clock duty cycle
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.............................................................................................................. 82 Changes from Revision A (December 2011) to Revision B
Page
Added note to RECOMMENDED OPERATING CONDITIONS
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Changed SUPPLY CHARACTERISTICS table
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Added RX and TX active, No input signal applied on ADC and DAC to Supply current, full duplex mode
test conditions
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Changed Power dissipation to Supply current in POWER IN CMOS MODE
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Added RX and TX active, No input signal applied on ADC and DAC to Supply current, full duplex mode
test conditions
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Added Power dissipation in Sleep modes MAX values
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Added (with MSB first format) to SPI REGISTER READOUT 3rd bullet
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