参数资料
型号: AGLE3000V2-FG896I
厂商: Microsemi SoC
文件页数: 32/166页
文件大小: 0K
描述: IC FPGA 1KB FLASH 3M 896-FBGA
标准包装: 27
系列: IGLOOe
逻辑元件/单元数: 75264
RAM 位总计: 516096
输入/输出数: 620
门数: 3000000
电源电压: 1.14 V ~ 1.575 V
安装类型: 表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 896-BGA
供应商设备封装: 896-FBGA(31x31)
IGLOOe Low Power Flash FPGAs
Revision 13
3-3
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected.
During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC
supplies continuously powered up, when the device transitions from programming to operating mode, the
I/Os are instantly configured to the desired user configuration.
Unused I/Os are configured as follows:
Output buffer is disabled (with tristate value of high impedance)
Input buffer is disabled (with tristate value of high impedance)
Weak pull-up is programmed
GL
Globals
GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the
global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have
identical capabilities. Unused GL pins are configured as inputs with pull-up resistors.
See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in Low Power
Flash Devices and Mixed Signal FPGAs" chapter of the IGLOOe FPGA Fabric User’s Guide. All inputs
labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input,
GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled GC/GF are
direct inputs into the chip-level globals, and the rest are connected to the quadrant globals. The inputs to
the global network are multiplexed, and only one input can be used as a global input.
Refer to the I/O Structure section of the IGLOOe FPGA Fabric User’s Guide for an explanation of the
naming of global pins.
FF
Flash*Freeze Mode Activation Pin
Flash*Freeze mode is available on IGLOOe devices. The FF pin is a dedicated input pin used to enter
and exit Flash*Freeze mode. The FF pin is active low, has the same characteristics as a single-ended
I/O, and must meet the maximum rise and fall times. When Flash*Freeze mode is not used in the design,
the FF pin is available as a regular I/O. The FF pin can be configured as a Schmitt trigger input.
When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering
Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted.
The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in
which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin
should be treated as a sensitive asynchronous signal. When defining pin placement and board layout,
simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be
considered.
Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both
Flash*Freeze mode and normal operation mode. No user intervention is required.
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AGLE3000V2-FGG484I 功能描述:IC FPGA 1KB FLASH 3M 484-FBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:IGLOOe 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP,带拉杆 供应商设备封装:352-CQFP(75x75)
AGLE3000V2-FGG896 功能描述:IC FPGA 1KB FLASH 3M 896-FBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:IGLOOe 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP,带拉杆 供应商设备封装:352-CQFP(75x75)
AGLE3000V2-FGG896ES 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology