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| 型号： | CP2201-GM |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 19/108页 |
| 文件大小： | 0K |
| 描述： | IC ETH CTRLR SNGL-CHIP 28QFN |
| 标准包装： | 73 |
| 控制器类型： | 以太网控制器，MAC/10Base-T |
| 接口： | 并行/串行 |
| 电源电压： | 3.1 V ~ 3.6 V |
| 电流 - 电源： | 75mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN（5x5） |
| 包装： | 管件 |
| 产品目录页面： | 627 (CN2011-ZH PDF) |
| 配用： | 336-1326-ND - KIT REF DESIGN PWR OVER ETHERNET 336-1316-ND - KIT EVAL FOR CP2201 ETH CTRLR |
| 其它名称： | 336-1313 |
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CP2200/1
18
Rev. 1.0
6. Functional Description
6.1. Overview
In most systems, the CP2200/1 is used for transmitting and receiving Ethernet packets, non-volatile data storage,
and controlling Link and Activity LEDs. The device is controlled using direct and indirect internal registers
accessible through the parallel host interface. All digital pins on the device are 5 V tolerant.
6.2. Reset Initialization
After every CP2200/1 reset, the following initialization procedure is recommended to ensure proper device
operation:
Step 1: Wait for the reset pin to rise. This step takes the longest during a power-on reset.
Step 2: Wait for Oscillator Initialization to complete. The host processor will receive notification through the
interrupt request signal once the oscillator has stabilized.
Step 3: Wait for Self Initialization to complete. The INT0 interrupt status register on page 31 should be
checked to determine when Self Initialization completes.
Step 4: Disable interrupts (using INT0EN and INT1EN on page 33 and page 36) for events that will not be
monitored or handled by the host processor. By default, all interrupts are enabled after every reset.
Step 5: Initialize the physical layer. See “15.7. Initializing the Physical Layer” on page 90 for a detailed
physical layer initialization procedure.
Step 6: Enable the desired Activity, Link, or Activity/Link LEDs using the IOPWR register on page 45.
Step 7: Initialize the media access controller (MAC). See “14.1. Initializing the MAC” on page 78 for a
detailed MAC initialization procedure.
Step 8: Configure the receive filter. See “12.4. Initializing the Receive Buffer, Filter and Hash Table” on
page 59 for a detailed initialization procedure.
Step 9: The CP2200/1 is ready to transmit and receive packets.
6.3. Interrupt Request Signal
The CP2200/1 has an interrupt request signal (INT) that can be used to notify the host processor of pending
interrupts. The INT signal is asserted upon detection of any enabled interrupt event. Host processors that cannot
dedicate a port pin to the INT signal can periodically poll the interrupt status registers to see if any interrupt
generating events have occurred. If the /INT signal is not used, pending interrupts such a Receive FIFO Full must
still be serviced.
The 14 interrupt sources are listed below. Interrupts are enabled on reset and can be disabled by software.
Pending interrupts can be cleared (allowing the INT signal to de-assert) by reading the self-clearing interrupt
registers. See “8. Interrupt Sources” on page 30 for a complete description of the CP2200/1 interrupts.
End of Packet Reached
Packet Received
Receive FIFO Empty
“Wake-on-LAN” Wakeup Event
Receive FIFO Full
Link Status Changed
Oscillator Initialization Complete
Jabber Detected
Self Initialization Complete
Auto-Negotiation Failed
Flash Write/Erase Complete
Remote Fault Notification
Packet Transmitted
Auto-Negotiation Complete
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