CP2201-GM (Silicon) PDF资料下载 Datasheet(40/108 页)

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参数资料

型号：	CP2201-GM
厂商：	Silicon Laboratories Inc
文件页数：	40/108页
文件大小：	0K
描述：	IC ETH CTRLR SNGL-CHIP 28QFN
标准包装：	73
控制器类型：	以太网控制器，MAC/10Base-T
接口：	并行/串行
电源电压：	3.1 V ~ 3.6 V
电流 - 电源：	75mA
工作温度：	-40°C ~ 85°C
安装类型：	表面贴装
封装/外壳：	28-VFQFN 裸露焊盘
供应商设备封装：	28-QFN（5x5）
包装：	管件
产品目录页面：	627 (CN2011-ZH PDF)
配用：	336-1326-ND - KIT REF DESIGN PWR OVER ETHERNET 336-1316-ND - KIT EVAL FOR CP2201 ETH CTRLR
其它名称：	336-1313

CP2200/1

Rev. 1.0

9. Reset Sources

Reset circuitry allows the CP2200/1 to be easily placed in a predefined default condition. Upon entry to this reset

state, the following events occur:

All direct and indirect registers are initialized to their defined reset values.

Digital pins (except /RST) are forced into a high impedance state with a weak pull-up to VDD.

Analog pins (TX+/TX–, RX+/RX–) are forced into a high impedance state without a weak pull-up.

The external oscillator is stopped and /RST driven low (except on a software reset).

All interrupts are enabled.

The contents of the transmit and receive buffers are unaffected by a reset as long as the device has maintained

sufficient supply voltage. However, since the buffer pointers are reset to their default values, the data is effectively

lost unless the host processor has kept track of the starting address and length of each packet in the buffer.

The CP2200/1 has five reset sources that place the device in the reset state. The method of entry to the reset state

determines the amount of time spent in reset and the behavior of the /RST pin. Each of the following reset sources

is described in the following sections:

Power-On

Power-Fail

Oscillator-Fail

External /RST Pin

Software Command

Upon exit from the reset state, the device automatically starts the external oscillator and waits for it to settle (this

step is skipped on software reset). Once the crystal oscillator settles, the Oscillator Initialization Complete interrupt

occurs (interrupt pin asserted), and the host processor may now access the internal registers to poll for the Self

Initialization Complete Interrupt. If the host does not have access to the interrupt signal, it should wait

approximately 1 ms after the rising edge of reset pin prior to polling the internal registers. Note that the reset pin

could remain low up to 100 ms depending on the power supply ramp time.

The device is fully functional after the Self Initialization has completed. See “6.2. Reset Initialization” on page 18 for

the recommended initialization procedure following a device reset.

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