参数资料
型号: DS2154LNA2+
厂商: Maxim Integrated Products
文件页数: 3/124页
文件大小: 0K
描述: IC TXRX E1 5V 100-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 90
类型: 收发器
驱动器/接收器数: 1/1
规程: E1
电源电压: 4.75 V ~ 5.25 V
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-LQFP(14x14)
包装: 托盘
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
100 of 124
18.
FUNCTIONAL TIMING DIAGRAMS
18.1.
Receive
Figure 18-1. Receive-Side Timing
Figure 18-2. Receive-Side Boundary Timing (with Elastic Store Disabled)
FRAME#
1
2
3456
789 10 11 12 13 14 15 16 1
4
RLINK
RLCLK
3
RSYNC
1
RSYNC
RFSYNC
2
NOTE 1: RSYNC IN FRAME MODE (RCR1.6 = 0).
NOTE 2: RSYNC IN MULTIFRAME MODE (RCR1.6 = 1).
NOTE 3: RLCLK IS PROGRAMMED TO OUTPUT JUST THE SA BITS.
NOTE 4: RLINK WILL ALWAYS OUTPUT ALL FIVE SA BITS AS WELL AS THE REST OF THE RECEIVE DATA STREAM.
NOTE 5: THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME.
CHANNEL 32
CHANNEL 1
CHANNEL 2
CHANNEL 32
CHANNEL 1
CHANNEL 2
RCLK
RSER
RSYNC
RFSYNC
RSIG
RCHCLK
RCHBLK
1
RLCLK
RLINK
2
CD
A
LSB
MSB
AB
Si
1
A Sa4 Sa5 Sa6 Sa7 Sa8
Sa4 Sa5 Sa6 Sa7 Sa8
B
Note 4
NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.
NOTE 2: RLCLK IS PROGRAMMED TO MARK THE SA4 BIT IN RLINK.
NOTE 3: SHOWN ISA RNAF FRAME BOUNDARY.
NOTE 4: RSIG NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1.
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