参数资料
| 型号： | DS2154LNA2+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 62/124页 |
| 文件大小： | 0K |
| 描述： | IC TXRX E1 5V 100-LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 90 |
| 类型： | 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | E1 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-LQFP（14x14） |
| 包装： | 托盘 |
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
42 of 124
CCR6: COMMON CONTROL REGISTER 6 (Address = 1D Hex)
(MSB)
(LSB)
LIUODO
CDIG
LIUSI
—
TCLKSRC
RESR
TESR
SYMBOL
POSITION
NAME AND DESCRIPTION
LIUODO
CCR6.7
Line Interface Open-Drain Option. This control bit determines whether
the TTIP and TRING outputs will be open drain or not. The line driver
outputs can be forced open drain to allow 6Vpeak pulses to be generated
or to allow the creation of a very low power interface.
0 = allow TTIP and TRING to operate normally
1 = force the TTIP and TRING outputs to be open drain
CDIG
CCR6.6
Customer Disconnect Indication Generator. This control bit
determines whether the Line Interface will generate an unframed
...1010... pattern at TTIP and TRING instead of the normal data pattern.
0 = generate normal data at TTIP and TRING as input via TPOSI and
TNEGI
1 = generates a ...1010... pattern at TTIP and TRING
LIUSI
CCR6.5
Line Interface G.703 Synchronization Interface Enable. This control
bit determines whether the line receiver should handle a normal E1 signal
(Section 6 of G.703) or a 2.048MHz synchronization signal (Section 10
of G.703). This control has no affect on the line interface transmitter.
0 = line receiver configured to support a normal E1 signal
1 = line receiver configured to support a synchronization signal
—
CCR6.4
Not Assigned. Should be set to zero when written.
—
CCR6.3
Not Assigned. Should be set to zero when written.
TCLKSRC
CCR6.2
Transmit Clock Source Select. This function allows the user to
internally select RCLK as the clock source for the transmit-side
formatter.
0 = Source of transmit clock determined by CCR2.2 (LOTCMC)
1 = Force transmitter to internally switch to RCLK as source of transmit
clock. Signal at TCLK pin is ignored
RESR
CCR6.1
Receive Elastic Store Reset. Setting this bit from a zero to a one will
force the receive elastic store to a depth of one frame. Receive data is lost
during the reset. Should be toggled after RSYSCLK has been applied and
is stable. Must be cleared and set again for a subsequent reset.
TESR
CCR6.0
Transmit Elastic Store Reset. Setting this bit from a zero to a one will
force the transmit elastic store to a depth of one frame. Transmit data is
lost during the reset. Should be toggled after TSYSCLK has been applied
and is stable. Must be cleared and set again for a subsequent reset.
相关PDF资料 |
PDF描述 |
|---|---|
| DS2154L | IC TXRX E1 1CHIP 5V ENH 100-LQFP |
| DS2155LN | IC TXRX T1/E1/J1 1-CHIP 100-LQFP |
| DS2156LN+ | IC TXRX T1/E1/J1 1-CHIP 100-LQFP |
| DS2172T/T&R | IC TESTER BIT ERROR RATE 32-TQFP |
| DS2174QN+ | IC BERT ENHANCED 44-PLCC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS2154LNA2+ | 功能描述:网络控制器与处理器 IC Enhanced E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS2154LND2 | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS2154LND2+ | 制造商:Maxim Integrated Products 功能描述:ENHANCED E1 SCT LQFP REVD2 IND LF - Rail/Tube |
| DS2155 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface |
| DS2155_06 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:T1/E1/J1 Single-Chip Transceiver |
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