参数资料
| 型号： | DS2154LNA2+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 92/124页 |
| 文件大小： | 0K |
| 描述： | IC TXRX E1 5V 100-LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 90 |
| 类型： | 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | E1 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-LQFP（14x14） |
| 包装： | 托盘 |
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
7 of 124
1.1.
Functional Description
The analog AMI/HDB3 waveform off the E1 line is transformer coupled into the RRING and RTIP pins
of the DS21354/554. The device recovers clock and data from the analog signal and passes it through the
jitter attenuation mux to the receive-side framer where the digital serial stream is analyzed to locate the
framing/multiframe pattern. The DS21354/DS21554 contain an active filter that reconstructs the analog-
received signal for the nonlinear losses that occur in transmission. The devices have a usable receive
sensitivity of 0 to -43dB, which allows the device to operate on cables over 2km in length. The receive-
side framer locates FAS frame and CRC and CAS multiframe boundaries as well as detects incoming
alarms including, carrier loss, loss of synchronization, AIS, and Remote Alarm. If needed, the receive-
side elastic store can be enabled to absorb the phase and frequency differences between the recovered E1
data stream and an asynchronous backplane clock, which is provided at the RSYSCLK input. The clock
applied at the RSYSCLK input can be either a 2.048MHz/4.096MHz/8.192MHz clock or a 1.544MHz
clock.
The transmit-side framer is totally independent from the receive side in both the clock requirements and
characteristics. Data off a backplane can be passed through a transmit-side elastic store if necessary. The
transmit formatter provides the necessary frame/multiframe data overhead for E1 transmission.
Reader’s Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In
each 125
ms frame, there are 32 eight-bit time slots numbered 0 to 31. Time slot 0 is transmitted first and
received first. These 32 time slots are also referred to as channels with a numbering scheme of 1 to 32.
Time slot 0 is identical to channel 1, time slot 1 is identical to Channel 2, and so on. Each time slot (or
channel) is made up of eight bits, which are numbered 1 to 8. Bit number 1 is the most significant bit
(MSB) and is transmitted first. Bit number 8 is the least significant bit (LSB) and is transmitted last. The
term “locked” refers to two clock signals that are phase or frequency locked, or derived from a common
clock (i.e., a 1.544MHz clock may be locked to a 2.048MHz clock if they share the same 8kHz
component). Throughout this data sheet, the following abbreviations are used:
NAME
FUNCTION
FAS
Frame-Alignment Signal
CAS
Channel-Associated Signaling
MF
Multiframe
Si
International Bits
CRC4
Cyclical Redundancy Check
CCS
Common-Channel Signaling
Sa
Additional Bits
E-Bit
CRC4 Error Bits
相关PDF资料 |
PDF描述 |
|---|---|
| DS2154L | IC TXRX E1 1CHIP 5V ENH 100-LQFP |
| DS2155LN | IC TXRX T1/E1/J1 1-CHIP 100-LQFP |
| DS2156LN+ | IC TXRX T1/E1/J1 1-CHIP 100-LQFP |
| DS2172T/T&R | IC TESTER BIT ERROR RATE 32-TQFP |
| DS2174QN+ | IC BERT ENHANCED 44-PLCC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS2154LNA2+ | 功能描述:网络控制器与处理器 IC Enhanced E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS2154LND2 | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS2154LND2+ | 制造商:Maxim Integrated Products 功能描述:ENHANCED E1 SCT LQFP REVD2 IND LF - Rail/Tube |
| DS2155 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface |
| DS2155_06 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:T1/E1/J1 Single-Chip Transceiver |
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