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| 型号： | DS3131 |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | Telecom IC:Other |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封装： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件页数： | 156/174页 |
| 文件大小： | 1261K |
| 代理商： | DS3131 |
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DS3131
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9.2.3 Free Queue
The host writes the 32-bit addresses of the available (free) data buffers and their associated packet
descriptors to the receive free queue. The descriptor space is indicated through a 16-bit pointer, which
the DMA uses along with the receive packet descriptor base address to find the exact 32-bit address of
the associated receive packet descriptor.
Figure 9-5. Receive Free-Queue Descriptor
dword 0
Free Data Buffer Address (32)
dword 1
Unused (16)
Free Packet Descriptor Pointer (16)
Note:
The organization of the free queue is not affected by the enabling of Big Endian.
dword 0; Bits 0 to 31/Data Buffer Address. Direct 32-bit starting address of a free data buffer.
dword 1; Bits 0 to 15/Free Packet Descriptor Pointer. This 16-bit value is the offset from the receive descriptor
base address of the free descriptor space associated with the free data buffer in dword 0.
dword 1; Bits 16 to 31/Unused. Not used by the DMA. Can be set to any value by the host and is ignored by the
receive DMA.
The receive DMA read from the receive free-queue descriptor circular queue, which data buffers and their
associated descriptors are available for use by the DMA.
The receive free-queue descriptor is actually a set of two circular queues (Figure 9-6). There is one circular queue
that indicates where free large buffers and their associated free descriptors exist. There is another circular queue
that indicates where free small buffers and their associated free descriptors exist.
Large and Small Buffer Size Handling
Through the receive configuration-RAM buffer-size field, the DMA knows for a particular HDLC
channel whether the incoming packets should be stored in the large or the small free data buffers. The
host informs the DMA of the size of both the large and small buffers through the receive large and small
buffer size (RLBS/RSBS) registers. For example, when the DMA knows that data is ready to be written
onto the PCI bus, it checks to see if the data is to be sent to a large buffer or a small buffer, and then it
goes to the appropriate free-queue descriptor and pulls the next available free buffer address and free
descriptor pointer. If the host wishes to have only one buffer size, then the receive free queue small-
buffer start address is set equal to the receive free-queue end address. In the receive configuration RAM,
none of the active HDLC channels are configured for the small buffer size.
There are a set of internal addresses within the device to keep track of the addresses of the dual circular
queues in the receive free queue. These are accessed by the host and the DMA. On initialization, the host
configures all of the registers shown in Table 9-E. After initialization, the DMA only writes to (changes)
the read pointers and the host only writes to the write pointers.
相关PDF资料 |
PDF描述 |
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| DS3134 | DATACOM, FRAMER, PBGA256 |
| DS3150QN | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150Q | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150TN | DATACOM, PCM TRANSCEIVER, PDIP48 |
| DS3150T | DATACOM, PCM TRANSCEIVER, PQFP48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS3131DK | 功能描述:通信集成电路 - 若干 RoHS:否 制造商:Maxim Integrated 类型:Transport Devices 封装 / 箱体:TECSBGA-256 数据速率:100 Mbps 电源电压-最大:1.89 V, 3.465 V 电源电压-最小:1.71 V, 3.135 V 电源电流:50 mA, 225 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Tube |
| DS3134 | 功能描述:IC CTRLR HDLC CHATEAU 256-BGA RoHS:否 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN（6x6） 包装:* 其它名称:Q6396337A |
| DS-313PIN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog Miscellaneous |
| DS-313-PIN | 功能描述:信号调节 RoHS:否 制造商:EPCOS 产品:Duplexers 频率:782 MHz, 751 MHz 频率范围: 电压额定值: 带宽: 阻抗:50 Ohms 端接类型:SMD/SMT 封装 / 箱体:2.5 mm x 2 mm 工作温度范围:- 30 C to + 85 C 封装:Reel |
| DS31400 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter |
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