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参数资料
型号： DS3131
厂商： MAXIM INTEGRATED PRODUCTS INC
元件分类： Telecom IC:Other
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封装： 27 X 27 MM, PLASTIC, BGA-256
文件页数： 37/174页
文件大小： 1261K
代理商： DS3131
DS3131
131 of 174
Register Name:
PRCC0
Register Description:
PCI Revision ID/Class Code Register 0
Register Address:
0x008h
LSB
Revision ID (Read Only/Set to 00h)
Class Code (Read Only/Set to 00h)
Class Code (Read Only/Set to 80h)
MSB
Class Code (Read Only/Set to 02h)
Bits 0 to 7/Revision ID. These read-only bits identify the specific device revision, which is selected by Dallas
Semiconductor.
Bits 8 to 15/Class Code Interface. These read-only bits identify the subclass interface value for the device and
are fixed at 00h. See Appendix D of PCI Local Bus Specification Revision 2.1 for details.
Bits 16 to 23/Class Code Subclass. These read-only bits identify the subclass value for the device and are fixed at
80h, which indicate “Other Network Controller.” See Appendix D of PCI Local Bus Specification Revision 2.1 for
details.
Bits 24 to 31/Class Code Base Class. These read-only bits identify the base class value for the device and are
fixed at 02h, which indicate “Network Controllers.” See Appendix D of PCI Local Bus Specification Revision 2.1
for details.
Register Name:
PLTH0
Register Description:
PCI Latency Timer/Header Type Register 0
Register Address:
0x00Ch
LSB
Cache Line Size
Latency Timer
Header Type (Read Only/Set to 80h)
MSB
BIST (Read Only/Set to 00h)
Bits 0 to 7/Cache Line Size. These read/write bits indicates the cache line size in terms of dwords. If the burst
size of a data read transaction exceeds this value, then the PCI block uses the memory read multiple command.
Valid settings are 04h (4 dwords), 08h, 10h, 20h, and 40h (64 dwords). Other settings are interpreted as 00h. These
bits are forced to 0 when a hardware reset is initiated through the PRST pin.
Bits 8 to 15/Latency Timer. These read/write bits indicate the value of the latency timer (in terms of the number
of PCI clocks) for use when the device is a bus master. These bits are forced to 0 when a hardware reset is initiated
through the PRST pin.
Bits 16 to 23/Header Type. These read-only bits are forced to 80h, which indicate a multifunction device.
Bits 24 to 31/Built-In Self-Test (BIST). These read-only bits are forced to 0.
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