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| 型号： | DS3131 |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | Telecom IC:Other |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封装： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件页数： | 34/174页 |
| 文件大小： | 1261K |
| 代理商： | DS3131 |
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DS3131
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10.2.1
Command Bits (PCMD0)
Bit 0/I/O Space Control (IOC). This read-only bit is forced to 0 by the device to indicate that it does not respond
to I/O space accesses.
Bit 1/Memory Space Control (MSC). This read/write bit controls whether or not the device responds to accesses
by the PCI bus to the memory space, which are the internal device configuration registers. When this bit is set to 0,
the device ignores accesses attempted to the internal configuration registers. When set to 1, the device allows
accesses to the internal configuration registers. This bit should be set to 0 when the local bus is operated in the
configuration mode. This bit is forced to 0 when a hardware reset is initiated through the PRST pin.
0 = ignore accesses to the internal device configuration registers
1 = allow accesses to the internal device configuration registers
Bit 2/Master Control (MASC). This read/write bit controls whether or not the device can act as a master on the
PCI bus. When this bit is set to 0, the device cannot act as a master. When it is set to 1, the device can act as a bus
master. This bit is forced to 0 when a hardware reset is initiated through the PRST pin.
0 = deny the device from operating as a bus master
1 = allow the device to operate as a bus master
Bit 3/Special Cycle Control (SCC). This read-only bit is forced to 0 by the device to indicate that it cannot
decode special cycle operations.
Bit 4/Memory Write and Invalidate Command Enable (MWEN). This read-only bit is forced to 0 by the
device to indicate that it cannot generate the memory write and invalidate command.
Bit 5/VGA Control (VGA). This read-only bit is forced to 0 by the device to indicate that it is not a VGA-
compatible device.
Bit 6/Parity Error Response Control (PARC). This read/write bit controls whether or not the device should
ignore parity errors. When this bit is set to 0, the device ignores any parity errors that it detects and continues to
operate normally. When this bit is set to 1, the device must act on parity errors. This bit is forced to 0 when a
hardware reset is initiated through the PRST pin.
0 = ignore parity errors
1 = act on parity errors
Bit 7/Address Stepping Control (STEPC). This read-only bit is forced to 0 by the device to indicate that it is not
capable of address/data stepping.
Bit 8/PCI System Error Control (PSEC). This read/write bit controls whether or not the device should enable
the PSERR output pin. When this bit is set to 0, the device disables the PSERR pin. When this bit is set to 1, the
device enables the PSERR pin. This bit is forced to 0 when a hardware reset is initiated through the PRST pin.
0 = disable the PSERR pin
1 = enable the PSERR pin
Bit 9/Fast Back-to-Back Master Enable (FBBEN). This read-only bit is forced to 0 by the device to indicate that
it is not capable of generating fast back-to-back transactions to different agents.
Bits 10 to 15/Reserved. These read-only bits are forced to 0 by the device.
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| DS3150Q | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150TN | DATACOM, PCM TRANSCEIVER, PDIP48 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS3131DK | 功能描述:通信集成电路 - 若干 RoHS:否 制造商:Maxim Integrated 类型:Transport Devices 封装 / 箱体:TECSBGA-256 数据速率:100 Mbps 电源电压-最大:1.89 V, 3.465 V 电源电压-最小:1.71 V, 3.135 V 电源电流:50 mA, 225 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Tube |
| DS3134 | 功能描述:IC CTRLR HDLC CHATEAU 256-BGA RoHS:否 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN（6x6） 包装:* 其它名称:Q6396337A |
| DS-313PIN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog Miscellaneous |
| DS-313-PIN | 功能描述:信号调节 RoHS:否 制造商:EPCOS 产品:Duplexers 频率:782 MHz, 751 MHz 频率范围: 电压额定值: 带宽: 阻抗:50 Ohms 端接类型:SMD/SMT 封装 / 箱体:2.5 mm x 2 mm 工作温度范围:- 30 C to + 85 C 封装:Reel |
| DS31400 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter |
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