参数资料
型号: EPM2210GF256A5N
厂商: ALTERA CORP
元件分类: PLD
英文描述: FLASH PLD, PBGA256
封装: 17 X 17 MM, 1 MM PITCH, LEAD FREE, FBGA-256
文件页数: 18/108页
文件大小: 1342K
代理商: EPM2210GF256A5N
Altera Corporation
2–9
March 2008
MAX II Device Handbook, Volume 1
MAX II Architecture
asynchronous load data input comes from the data3 input of the LE. For
combinational functions, the LUT output bypasses the register and drives
directly to the LE outputs.
Each LE has three outputs that drive the local, row, and column routing
resources. The LUT or register output can drive these three outputs
independently. Two LE outputs drive column or row and DirectLink
routing connections and one drives local interconnect resources. This
allows the LUT to drive one output while the register drives another
output. This register packing feature improves device utilization because
the device can use the register and the LUT for unrelated functions.
Another special packing mode allows the register output to feed back into
the LUT of the same LE so that the register is packed with its own fan-out
LUT. This provides another mechanism for improved fitting. The LE can
also drive out registered and unregistered versions of the LUT output.
LUT Chain and Register Chain
In addition to the three general routing outputs, the LEs within an LAB
have LUT chain and register chain outputs. LUT chain connections allow
LUTs within the same LAB to cascade together for wide input functions.
Register chain outputs allow registers within the same LAB to cascade
together. The register chain output allows an LAB to use LUTs for a single
combinational function and the registers to be used for an unrelated shift
register implementation. These resources speed up connections between
LABs while saving local interconnect resources. Refer to “MultiTrack
Interconnect” on page 2–15 for more information about LUT chain and
register chain connections.
addnsub Signal
The LE’s dynamic adder/subtractor feature saves logic resources by
using one set of LEs to implement both an adder and a subtractor. This
feature is controlled by the LAB-wide control signal addnsub. The
addnsub
signal sets the LAB to perform either A + B or A – B. The LUT
computes addition; subtraction is computed by adding the two’s
complement of the intended subtractor. The LAB-wide signal converts to
two’s complement by inverting the B bits within the LAB and setting
carry-in to 1, which adds one to the least significant bit (LSB). The LSB of
an adder/subtractor must be placed in the first LE of the LAB, where the
LAB-wide addnsub signal automatically sets the carry-in to 1. The
Quartus II Compiler automatically places and uses the adder/subtractor
feature when using adder/subtractor parameterized functions.
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相关代理商/技术参数
参数描述
EPM2210GF256C3 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM2210GF256C3N 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM2210GF256C4 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM2210GF256C4N 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM2210GF256C5 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100