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参数资料
型号： EPM2210GF256A5N
厂商： ALTERA CORP
元件分类： PLD
英文描述： FLASH PLD, PBGA256
封装： 17 X 17 MM, 1 MM PITCH, LEAD FREE, FBGA-256
文件页数： 57/108页
文件大小： 1342K
代理商： EPM2210GF256A5N
3–2
Core Version a.b.c variable
Altera Corporation
MAX II Device Handbook, Volume 1
December 2007
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
w
Unsupported JTAG instructions should not be issued to the
MAX II device as this may put the device into an unknown state,
requiring a power cycle to recover device operation.
USERCODE
00 0000 0111
Selects the 32-bit USERCODE register and places it between
the TDI and TDO pins, allowing the USERCODE to be serially
shifted out of TDO. This register defaults to all 1’s if not
specified in the Quartus II software.
IDCODE
00 0000 0110
Selects the IDCODE register and places it between TDI and
TDO
, allowing the
IDCODE to be serially shifted out of TDO.
HIGHZ
(1)
00 0000 1011
Places the 1-bit bypass register between the TDI and TDO
pins, which allows the boundary scan test data to pass
synchronously through selected devices to adjacent devices
during normal device operation, while tri-stating all of the I/O
pins.
CLAMP
(1)
00 0000 1010
Places the 1-bit bypass register between the TDI and TDO
pins, which allows the boundary scan test data to pass
synchronously through selected devices to adjacent devices
during normal device operation, while holding I/O pins to a
state defined by the data in the boundary-scan register.
USER0
00 0000 1100
This instruction allows you to define the scan chain between
TDI
and TDO in the MAX II logic array. This instruction is also
used for custom logic and JTAG interfaces.
USER1
00 0000 1110
This instruction allows you to define the scan chain between
TDI
and TDO in the MAX II logic array. This instruction is also
used for custom logic and JTAG interfaces.
IEEE 1532 instructions
(2)
IEEE 1532 ISC instructions used when programming a MAX II
device via the JTAG port.
Notes to Table 3–1:
(1)
HIGHZ
, CLAMP, and EXTEST instructions do not disable weak pull-up resistors or bus hold features.
(2)
These instructions are shown in the 1532 BSDL files, which will be posted on the Altera website at
www.altera.com when they are available.
Table 3–1. MAX II JTAG Instructions (Part 2 of 2)
JTAG Instruction
Instruction Code
Description
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相关代理商/技术参数
参数描述
EPM2210GF256C3 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM2210GF256C3N 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM2210GF256C4 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM2210GF256C4N 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM2210GF256C5 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
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