参数资料
型号: EPM2210GF256A5N
厂商: ALTERA CORP
元件分类: PLD
英文描述: FLASH PLD, PBGA256
封装: 17 X 17 MM, 1 MM PITCH, LEAD FREE, FBGA-256
文件页数: 90/108页
文件大小: 1342K
代理商: EPM2210GF256A5N
5–12Core Version a.b.c variable
Altera Corporation
MAX II Device Handbook, Volume 1
July 2008
Timing Model and Specifications
Performance
Table 5–14 shows the MAX II device performance for some common
designs. All performance values were obtained with the Quartus II
software compilation of megafunctions. Performance values for –3, –4,
and –5 speed grades are based on an EPM1270 device target while –6 and
–7 speed grades are based on an EPM570Z device target.
Table 5–14. MAX II Device Performance
Resource
Used
Design Size and
Function
Resources Used
Performance
Unit
Mode
LEs
UFM
Blocks
–3
Speed
Grade
–4
Speed
Grade
–5
Speed
Grade
–6
Speed
Grade
–7
Speed
Grade
LE
16-bit counter (1)
16
0
304.0
247.5
201.1
184.1
123.5
MHz
64-bit counter (1)
64
0
201.5
154.8
125.8
83.2
MHz
16-to-1
multiplexer
11
0
6.0
8.0
9.3
17.4
17.3
ns
32-to-1
multiplexer
24
0
7.1
9.0
11.4
12.5
22.8
ns
16-bit XOR
function
5
0
5.1
6.6
8.2
9.0
15.0
ns
16-bit decoder
with single
address line
5
0
5.2
6.6
8.2
9.2
15.0
ns
UFM
512 × 16
None
3
1
10.0
MHz
512 × 16
SPI (2)
37
1
8.0
9.7
MHz
512 × 8
Parallel
73
1
MHz
512 × 16
I2C (3)
142
1
100 (5)
kHz
Notes to Table 5–14:
(1)
This design is a binary loadable up counter.
(2)
This design is configured for read-only operation in Extended mode. Read and write ability increases the number
of LEs used.
(3)
This design is configured for read-only operation. Read and write ability increases the number of LEs used.
(4)
This design is asynchronous.
(5)
The I2C megafunction is verified in hardware up to 100-kHz serial clock line (SCL) rate.
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