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| 型号： | GT- 32090 |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Highly Integrated Single-Chip System Controller(高集成单片系统控制器) |
| 中文描述： | 高度集成的单芯片系统控制器（高集成单片系统控制器） |
| 文件页数： | 11/67页 |
| 文件大小： | 524K |
| 代理商： | GT- 32090 |
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GT-32090 System Controller For i960JX Processors
19
Galileo
Technology, Inc.
3.6 DRAM Parameters
This register specifies the DRAM timing parameters and the DRAM’s refresh type support. The parameter BanknRef
which configures the refresh type support, can be set for each DRAM bank independently. The DRAM state machines
are optimized to different bus frequencies. In order to control the number of cycles to first data, the ADFreq bits should
be set according to the bus frequency.
DRAM Parameters, Offset: 0x424
3.7 Device Parameters
Device parameters can be different for each bank. The shape of the different control signals that are active in a device
access can be programmed. The access time (in number of cycles) of the device during read accesses should be pro-
grammed into the AccToFirst field, to set the time data from the device will be ready to be sampled by the CPU or by
the GT-32090. AccToNext should be programmed with the time data from the device can be sampled in consecutive
accesses during burst accesses. The DevCS* will be deasserted after the last data is latched and to prevent bus con-
tention the TurnOff field specifies the number of cycles (from the deassertion of DevCS*) to the beginning of the next
bus transaction. The write signals pulse can be shaped as well. The parameters specify the number of cycles from the
Bits
Field name
Function
Initial Value
0
Type
DRAM type used.
0 - Standard page mode
1 - EDO
0x0
1
Latch
Defines whether the DRAM has an external latch on
its data lines or not.
0 - No external latch
1 - With external latch
0x0
3:2
ADFreq
Processor bus frequency.
00 - 16MHz
01 - 20MHz
10 - 25MHz
11 - 33MHz
0x11
5:4
Bank0Ref
DRAM refresh type support.
00 - 1/2K Refresh (9 bits row, 9 to 11 bits column)
01 - 1K Refresh (10 bits row, 9 to 11 bits column)
10 - 2K Refresh (11 bits row, 9 to 11 bits column)
11 - Not used
0x0
7:6
Bank1Ref
DRAM refresh type support.
00 - 1/2K Refresh (9 bits row, 9 to 11 bits column)
01 - 1K Refresh (10 bits row, 9 to 11 bits column)
10 - 2K Refresh (11 bits row, 9 to 11 bits column)
11 - Not used
0x0
9:8
Bank2Ref
DRAM refresh type support.
00 - 1/2K Refresh (9 bits row, 9 to 11 bits column)
01 - 1K Refresh (10 bits row, 9 to 11 bits column)
10 - 2K Refresh (11 bits row, 9 to 11 bits column)
11 - Not used
0x0
11:10
Bank3Ref
DRAM refresh type support.
00 - 1/2K Refresh (9 bits row, 9 to 11 bits column)
01 - 1K Refresh (10 bits row, 9 to 11 bits column)
10 - 2K Refresh (11 bits row, 9 to 11 bits column)
11 - Not used
0x0
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