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| 型号： | GT- 32090 |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Highly Integrated Single-Chip System Controller(高集成单片系统控制器) |
| 中文描述： | 高度集成的单芯片系统控制器（高集成单片系统控制器） |
| 文件页数： | 5/67页 |
| 文件大小： | 524K |
| 代理商： | GT- 32090 |
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GT-32090 System Controller For i960JX Processors
13
Galileo
Technology, Inc.
3 REGISTER TABLES
The GT-32090’s internal registers are memory mapped and can be accessed by the CPU. The registers’ address is
comprised of the value in the Internal Address Space Decode and Control register and the register’s Offset. For exam-
ple, to access the “Channel 0 DMA Byte Count” register (Offset 0x800) immediately after reset, assuming that during
reset DMAAck[2:0]*’s value was “110”, the following occurs: the value in the “Internal Address Space Decode and Con-
trol” register bits [5:0] will be “0x33”, which must match the AD bus bits [31:26] as “110011”, and the offset being 0x800,
will result in a 32-bit address of 0xcc000800. The location of the registers in the memory space can be changed by
changing the value programmed into the Internal Address Space Decode and Control register. For example, after
changing the value in this register by writing to 0xcc00001c a value of “0x28”, an access to the “Channel 0 DMA Byte
Count” register will be with 0xa0000800.
The GT-32090’s internal registers are 32-bits wide and consequently the appropriate memory region must be config-
ured as a 32-bits region, which is done by programming the CPU’s appropriate PMCON register.
3.1
Register Map
Description
Offset
Group Address Space
DRAM Address Space
0x000
Device 0 Address Space
0x004
Device 1 Address Space
0x008
Device 2 Address Space
0x00c
Boot Device Address Space
0x010
SIO Address Space
0x014
PCMCIA Address Space
0x018
Internal Address Space Decode and Control
0x01c
DRAM Address Space
RAS[0] Decode Address
0x400
RAS[1] Decode Address
0x404
RAS[2] Decode Address
0x408
RAS[3] Decode Address
0x40c
Device Address Space
CS[0] Decode Address
0x410
CS[1] Decode Address
0x414
CS[2] Decode Address
0x418
BootCS Decode Address
0x41c
DRAM Refresh Configuration
Refresh Configuration
0x420
DRAM Parameters
DRAM Parameters
0x424
Device Parameters
Device Bank0 Parameters
0x428
Device Bank1 Parameters
0x42c
Device Bank2 Parameters
0x430
Device Boot Bank Parameters
0x434
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