- 您现在的位置：买卖IC网 > PDF目录67672 > GT- 32090 (Galileo Technology Services, LLC) Highly Integrated Single-Chip System Controller(高集成单片系统控制器) PDF资料下载
参数资料
| 型号： | GT- 32090 |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Highly Integrated Single-Chip System Controller(高集成单片系统控制器) |
| 中文描述： | 高度集成的单芯片系统控制器（高集成单片系统控制器） |
| 文件页数： | 45/67页 |
| 文件大小： | 524K |
| 代理商： | GT- 32090 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页当前第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页
GT-32090 System Controller For i960JX Processors
5
Galileo
Technology, Inc.
Ready*
I
Ready: When not active, it extends the access to a device on the
AD bus by adding wait cycles.
BufOE*
O
Buffer Output Enable: This signal has similar functionality to the
DEN* signal of the i960JX, but is active during accesses to devices
only. It is active during the data phase of accesses to devices on the
AD bus. It is used with the W/R* to control external data transceiv-
ers.
PCMCIA & SIO
Shared Signals
P/SAddr[1:0]
O
PCMCIA/SIO Address: Byte and half-word addresses for PCMCIA
and SIO accesses.
P/SData[15:0]
I/O
Data Bus: Shared data bus for SIO and PCMCIA devices.
SIO Interface
SBE[1:0]*
O
SIO Byte Enable: Selects which of the two bytes on the SIO bus
participates in the current data transfer.
SCS[3:0]*
O
SIO Chip Select: Chip Select for devices on the SIO bus.
SRd*
O
SIO Read: Active during a read from a device on the SIO bus.
SWr*
O
SIO Write: Active during a write to a device on the SIO bus.
SWait*
I
SIO Wait: Extends bus cycle, used to generate wait states by SIO
devices.
PCMCIA Card A
CardEnA[2:1]*
O
Card Enable A: CardEnA[1] enables the even address bytes, and
CardEnA[2] enables the odd address bytes.
OEA*
O
Output Enable A: Controls the output of data from card.
WaitA*
I
Wait A: Extends bus cycle, used to generate wait states by the
card.
WrEnA*
O
Write Enable A: Indicates write accesses by the GT-32090 to the
card.
IORdA*
O
I/O Read A: Activated to read data from the card’s I/O space.
IOWrA*
O
I/O Write A: Activated to write data to the card’s I/O space.
PCMCIA Card B
CardEnB[2:1]*
O
Card Enable B: CardEnB[1] enables the even address bytes, and
CardEnB[2] enables the odd address bytes.
OEB*
O
Output Enable B: Controls the output of data from card.
WaitB*
I
Wait B: Extends bus cycle, used to generate wait states by the
card.
WrEnB*
O
Write Enable B: Indicates write accesses by the GT-32090 to the
card.
IORdB*
O
I/O Read B: Activated to read data from the card’s I/O space.
IOWrB*
O
I/O Write B: Activated to write data to the card’s I/O space.
DMA
ADBusReq
I
Bus Request: Signals a request from the external agent to the GT-
32090 for acquisition of the AD bus.
Pin Name
Type
Description
相关PDF资料 |
PDF描述 |
|---|---|
| GT-48001A | Switched Ethernet Controller For 10BaseX(10BaseX交换式快速以太网控制器) |
| GT-48002A | Switched Fast Ethernet Controller for 100BaseX(100BaseX交换式快速以太网控制器) |
| GT-48004A | Four Port Switched Fast Ethernet Controller(四端口、交换式快速以太网控制器) |
| GT-48006A | Low Cost Two Port 10/100Mbps Ethernet Bridge/Switch Controller(低成本、双端口10/100Mbps以太网桥式/交换式控制器) |
| GT-48207 | Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高级交换式 10+10/100 BaseX以太网控制器) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GT-32090-A0-PBN-C000 | 制造商:Marvell 功能描述: |
| GT3-20DP-2.5DSA | 制造商:HRS 制造商全称:HRS 功能描述:Antenna, Sensor, and Communications Trunk Line Connections |
| GT321 | 制造商:CORNELL DUBILIER ELECTRONICS 功能描述:Cap Ceramic 220pF 3000V SL 5% (20 X 6mm) Radial 9.5mm 85°C |
| GT32-10P-1.5H | 制造商:Hirose 功能描述: |
| GT32-10S-6/CR-MP | 制造商:Hirose 功能描述:902-5118-4-00 EACH 制造商:Hirose 功能描述:GT32-10S-6/CR-MP |
发布紧急采购，3分钟左右您将得到回复。