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| 型号： | GT- 32090 |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Highly Integrated Single-Chip System Controller(高集成单片系统控制器) |
| 中文描述： | 高度集成的单芯片系统控制器（高集成单片系统控制器） |
| 文件页数： | 2/67页 |
| 文件大小： | 524K |
| 代理商： | GT- 32090 |
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GT-32090 System Controller For i960JX Processors
10
Galileo
Technology, Inc.
The SWait* pin is used to extend a data cycle. Two cycles
prior to the end of an access, SWait* is sampled. If it is
asserted, then the access is extended. When SWait* is
again deasserted, two more cycles will be executed until
the end of the data transfer.
Standard address space is 64MBytes. Each of the Chip
Select signals has a 16 MByte address space, can be
configured as 8-bit or 16-bit wide, and has programmable
timing. Big and little endian conversion is supported for
each device. The SIO supports up to three slave DMA
devices as described in section 2.5. Further sub-decod-
ing can result in four Chip Selects for a total of 128
MBytes of address space.
Timing for an SIO bus DMA or CPU access is program-
mable. The user can specify the width of active SRd* and
SWr* signals, and the Turn-Off time of the device. The
width of SRd* and SWr* dictate the shapes of SCS* and
DMAAck*. They are asserted one cycle before SRd* or
SWr* become active, and remain active for one cycle
after SRd* or SWr* is deasserted. The GT-32090 will not
start a new read cycle from a different SIO device and will
not start a new write access on the SIO bus as long as
the Turn-Off time is not satisfied. The Turn-Off Width will
start counting when SCS* is deasserted to terminal
count.
When the channel is programmed to Word arbitration, a
device will be served until all the remaining bytes are
packed/unpacked. Between accesses, DMAAck* will be
deasserted for 1 cycle and SWr* /SRd* for 3 cycles.
When the channel is programmed to Burst Mode with
Word arbitration, DMAAck* will stay asserted through the
entire burst. It will be asserted one cycle before SRd* (or
SWr*) becomes active, and remain asserted until one
cycle after the last SRd* (or SWr*) of the burst is deas-
serted. The SRd* or SWr* signals will be asserted for the
number of clocks programmed in PulsWid and deas-
serted for one clock.
The partition between the devices is fixed and decoding
in the SIO is done on address bits 25:24.
SCS[0]* : Address[25:24] = 00
SCS[1]* : Address[25:24] = 01
SCS[2]* : Address[25:24] = 10
SCS[3]* : Address[25:24] = 11
2.7
PCMCIA
Two PCMCIA cards can be supported directly by the GT-
32090. Each card has a 128MByte address space dedi-
cated to it, 64MBytes for I/O space and 64MBytes for
memory space. There is support for big or little endian
data formats and 8-bit or 16-bit accesses. The timing of
the control signals to the cards is programmable. All the
control signals between the cards and the GT-32090 can
be connected without glue logic except for the static con-
trol and status signals. They are interfaced to the GT-
32090 through an external latch and buffer, as shown in
the application section.
The partition between PCMCIA devices is fixed and
decoding is done on address bits 27:26.
PCMCIAa Memory : Address[27:26] = 00
PCMCIAa I/O
: Address[27:26] = 01
PCMCIAb Memory : Address[27:26] = 10
PCMCIAb I/O
: Address[27:26] = 11
2.8 JTAG (Boundary Scan)
The GT-32090 supports JTAG test features compatible
with the IEEE Standard Test Access Port And Boundary
Scan Architecture (IEEE 1149.1.A).
The JTAG features supported are:
The GT-32090 IDCode is 03290115h.
Bit[31:28] : Version: ‘0000’
Bit[27:12] : Part Number: ‘0011001010010000’
Bit[11:1] : Manufacturer ID: ‘00010001010’
Bit[0] : IDCode’s bit[0] is ‘1’ by definition.
Boundary Scan Pins Order:
All the control signals are active LOW, that is, the output
is enabled when its control signal is "0".
Test Name
Binary Code
EXTEST
000
SAMPLE
010
IDCODE
001
STCTST
101
INTEST
100
BYPASS
111
pad signal
chain
pos
pad
type
scan
type
control signal
-
[145]
ctrl
norm
s_io_oe_buf3_Z
P/SData[0]
[144]
bidir
norm
s_io_oe_buf3_Z
P/SData[1]
[143]
bidir
norm
s_io_oe_buf3_Z
P/SData[2]
[142]
bidir
norm
s_io_oe_buf3_Z
P/SData[3]
[141]
bidir
norm
s_io_oe_buf3_Z
P/SData[4]
[140]
bidir
norm
s_io_oe_buf3_Z
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