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参数资料
| 型号： | GT- 32090 |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Highly Integrated Single-Chip System Controller(高集成单片系统控制器) |
| 中文描述： | 高度集成的单芯片系统控制器（高集成单片系统控制器） |
| 文件页数： | 56/67页 |
| 文件大小： | 524K |
| 代理商： | GT- 32090 |
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GT-32090 System Controller For i960JX Processors
6
Galileo
Technology, Inc.
ADBusGnt
O
Bus Grant: Signals that the GT-32090 grants mastership on the AD
bus to the external agent.
DMAReq[2:0]
I
DMA Request: A request for a DMA operation directed at the inter-
nal arbiter. When Rst* is asserted these bits are sampled into the
Device Address Space register bits [6:4].
DMAAck[2:0]*
I/O
DMA Acknowledgement:
Outputs - The internal arbiter grants a DMA operation to a request-
ing device.
Inputs - When Rst* is asserted, these bits are sampled into the
Internal Space Decode & Control register bits [5:3].
These pins are inputs when Rst* is active, until 2 clocks after Rst* is
deasserted. They are outputs at all other times.
DMAInt[2:0]*
O
Interrupt: Each interrupt corresponds to one of the DMA channels.
Miscellaneous
Rst*
I
Reset: Resets all internal logic and state machines to a known
state.
Clock
I
Clock: The input clock to the GT-32090.
JTAG
JTDI
I
Test Data Input Pin: JTAG’s serial input
JTMS
I
Test Mode Select: Used to issue serial instructions to the TAP con-
troller’s state machine.
JTClk
I
Test Clock: JTAG’s input clock
JTRst*
I
Test Reset: Active low asynchronous reset for the TAP controller
JTDO
O
Test Data Output: JTAG’s serial output
SCAN
Test*
I
Test: When active, indicates that the GT-32090 is in Scan mode.
0 - Scan mode
1 - Normal operation
HiZAll*
I
Tri-State: When active, the GT-32090 drives all outputs and I/O
pins to High impedance.
0 - Tri-State
1 - Normal operation
Pin Name
Type
Description
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| GT-32090-A0-PBN-C000 | 制造商:Marvell 功能描述: |
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