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| 型号： | GT- 32090 |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Highly Integrated Single-Chip System Controller(高集成单片系统控制器) |
| 中文描述： | 高度集成的单芯片系统控制器（高集成单片系统控制器） |
| 文件页数： | 65/67页 |
| 文件大小： | 524K |
| 代理商： | GT- 32090 |
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GT-32090 System Controller For i960JX Processors
7
Galileo
Technology, Inc.
2
FUNCTIONAL DESCRIPTION
2.1
CPU Interface
The GT-32090 has a glueless interface to the Intel
i960JX family of processors with bus frequencies
between 16MHz and 33MHz. External agents can take
control of the AD bus and access all of the GT-32090
resources. The GT-32090 handles the priorities between
the internal DMA resources, the CPU and the external
agent. It will request the AD bus from the CPU and relin-
quish the bus to the external agent. For systems that
need extension of the capabilities offered by the GT-
32090, up to four GT-32090 devices can support one
CPU. For example, with four GT-32090’s, the system can
have up to 512MBytes of DRAM and 12 DMA channels.
2.2
Address Space Decode
The GT-32090 decodes the address space in two stages.
In the first stage, the decoding is done to eight groups
that include the following: four spaces of 32 MBytes for
the AD bus devices, 128 MBytes for the DRAM, 128
MBytes for the Simple I/O bus (SIO bus), 256 MBytes for
the PCMCIA, and 64 MBytes for the internal address
space. The decoding in the first stage is done by compar-
ing the high order address bits with the Address Space
registers’ values. This way, four groups of devices are
provided in order to enable mappings of 8-, 16- and 32-
bit devices in the same system, using different PMCONs
(PMCONs are the i960JX’s Physical Memory Configura-
tion registers - see i960JX User’s Manual). In the second
stage, there is additional decoding to the specific device
bank, DRAM bank, internal register, SIO bank, or PCM-
CIA bank. The sub-decoding for the DRAM and the AD
bus device banks is programmable while the sub-decod-
ing for the internal registers, the PCMCIA cards, and the
SIO devices, is fixed.
Each DRAM bank can have a programmable address
space of 1MByte to 16MBytes that can be located any-
where in the DRAM address space. The address space
size programmability enables a contiguous address
space when accessing the different DRAM banks even
when the banks have different sizes. The decoding is
done by comparing address bits 25:20 to be between two
values (High and Low) in the DRAM bank registers.
Each AD bus device bank can have a programmable
address space of 2MBytes to 32MBytes. Similar to the
DRAM banks, it enables a contiguous address space for
different AD device bank sizes. The decoding is done by
comparing address bits 24:21 to be between two values
(High and Low) in the AD device bank registers.
The PCMCIA is allocated a 256MByte block that has a
fixed sub-decoding to four 64MByte spaces. The first
128MBytes are allocated to card A and the second
128MBytes to card B. Each 128MBytes are divided so
that the first 64MBytes are for memory space and the
second 64MBytes are for I/O address space.
The SIO space is sub-decoded to four fixed 16 MByte
spaces for the SIO Chip Selects, or eight 16MByte
spaces with external sub-decoding to create a 128MByte
space.
The internal address space is sub-decoded for the con-
trol and status registers that reside on the GT-32090.
The GT-32090 will not respond to addresses that are not
allocated to it, since that address space might be used
for other devices.
2.3
DRAM Controller
The DRAM controller supports 4 banks of page mode or
EDO DRAMs. DRAM types supported are those with
0.5K, 1K, and 2K refresh, as well as asymmetric RAS/
CAS addressing. The depth of the DRAM devices can
vary for each bank separately from 256K to 4M, and the
width of all banks is 32-bits. With these options, each
DRAM bank size can vary from 1MByte to 16MBytes.
The DRAM timing is optimized for the different frequen-
cies and device types supported. There is optional sup-
port for an external bi-directional latch on the DRAM’s
data bus for improved DRAM performance.
At 33MHz, a CPU read access from an EDO DRAM will
have the pattern xxDDDD, which means 2 wait-states to
first data and zero wait-state for each additional word. At
33MHz, with standard DRAMs, the pattern will be
xxDxDxDxDx, meaning 2 wait-states to the first data and
1 wait-state for each additional word. At 25MHz, standard
DRAM with latch or EDO DRAM will have a performance
of xDDDD (one wait-state to first data). At 25MHz, stan-
dard DRAM without latches will be xxDxDxDxDx (2 wait-
states to first data, 1 wait-state to burst data. At 20MHz
and 16MHz using standard DRAM with latches or EDO
DRAM, the pattern will be DDDD, zero wait-states to the
first data and zero wait-states for each additional word. At
20MHz and 16MHz, DRAM performance is
xxDxDxDxDx. DMA burst accesses can be one per clock,
using the same parameters as for the CPU access.
Refresh can be programmed to different periods by a 16-
bit refresh counter. Staggered and non-staggered refresh
modes are supported. In staggered mode, the four banks
of DRAM will be refreshed with one cycle delay between
each bank, while in non-staggered mode all four banks
will be refreshed together.
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