375
14.3
Operation
14.3.1
Watchdog Timer Operation
To use the WDT as a watchdog timer, set the WT/
,7 and TME bits in TCSR to 1. Software must
prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before
overflow occurs. This ensures that TCNT does not overflow while the system is operating
normally. If TCNT overflows without being rewritten because of a system crash or other error,
an internal reset or NMI interrupt request is generated.
When the RST/
10, bit is set to 1, the chip is reset for 518 system clock periods (518 ) by a
counter overflow. This is illustrated in figure 14.3.
When the RST/
10, bit cleared to 0, an NMI interrupt request is generated by a counter
overflow.
An internal reset request from the watchdog timer and reset input from the
5(6 pin are handled
via the same vector. The reset source can be identified from the value of the XRST bit in
SYSCR.
If a reset caused by an input signal from the
5(6 pin and a reset caused by WDT overflow occur
simultaneously, the
5(6 pin reset has priority, and the XRST bit in SYSCR is set to 1.
An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin
are handled via the same vector. Simultaneous handling of a watchdog timer NMI interrupt
request and an NMI pin interrupt request must therefore be avoided.
TCNT value
H'00
Time
H'FF
WT/
IT = 1
TME = 1
H'00 written
to TCNT
WT/
IT = 1
TME = 1
H'00 written
to TCNT
518 system clock periods
Internal reset signal
Overflow
OVF = 1*
WT/
IT: Timer mode select bit
TME:
Timer enable bit
OVF:
Overflow flag
Note: * Cleared to 0 by an internal reset when OVF is set to 1. XRST is cleared to 0.
Figure 14.3 Operation in Watchdog Timer Mode