64
2.8.2
Reset State
When the
5(6 input goes low all current processing stops and the CPU enters the reset state. All
interrupts are disabled in the reset state. Reset exception handling starts when the
5(6 signal
changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, refer to section 14,
Watchdog Timer.
2.8.3
Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address
(vector) from the exception vector table and branches to that address.
Types of Exception Handling and Their Priority: Exception handling is performed for resets,
interrupts, and trap instructions. Table 2.7 indicates the types of exception handling and their
priority. Trap instruction exception handling is always accepted in the program execution state.
Exception handling and the stack structure depend on the interrupt control mode set in SYSCR.
Table 2.7
Exception Handling Types and Priority
Priority
Type of Exception
Detection Timing
Start of Exception Handling
High
Reset
Synchronized with clock
Exception handling starts
immediately after a low-to-high
transition at the
5(6 pin, or
when the watchdog timer
overflows.
Interrupt
End of instruction
execution or end of
exception-handling
sequence*
1
When an interrupt is requested,
exception handling starts at the
end of the current instruction or
current exception-handling
sequence.
Low
Trap instruction
When TRAPA instruction
is executed
Exception handling starts when
a trap (TRAPA) instruction is
executed.*
2
Notes: 1. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC
instructions, or immediately after reset exception handling.
2. Trap instruction exception handling is always accepted in the program execution state.