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14.5.2
Changing Value of CKS2 to CKS0
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the value of bits CKS2 to CKS0.
14.5.3
Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is
operating, errors could occur in the incrementation. Software must stop the watchdog timer (by
clearing the TME bit to 0) before switching the mode.
14.5.4
Counter Value in Transitions between High-Speed Mode, Subactive Mode, and
Watch Mode
If the mode is switched between high-speed mode and subactive mode or between high-speed
mode and watch mode when WDT1 is used as a realtime clock counter, an error will occur in
the counter value when the internal clock is switched.
When the mode is switched from high-speed mode to subactive mode or watch mode, the
increment timing is delayed by approximately 2 or 3 clock cycles when the WDT1 control clock
is switched from the main clock to the subclock.
Also, since the main clock oscillator is halted during subclock operation, when the mode is
switched from watch mode or subactive mode to high-speed mode, the clock is not supplied
until internal oscillation stabilizes. As a result, after oscillation is started, counter incrementing
is halted during the oscillation stabilization time set by bits STS2 to STS0 in SBYCR, and there
is a corresponding discrepancy in the counter value.
Caution is therefore required when using WDT1 as the realtime clock counter.
No error occurs in the counter value while WDT1 is operating in the same mode.