778
LPWRCR—Low-Power Control Register
H'FF85
System
7
DTON
0
R/W
6
LSON
0
R/W
5
NESEL
0
R/W
4
EXCLE
0
R/W
3
—
0
—
0
—
0
—
2
—
0
—
1
—
0
—
Bit
Initial value
Read/Write
Subclock input enable
0
Subclock input from EXCL pin is disabled
1
Subclock input from EXCL pin is enabled
Noise elimination sampling frequency select
0
Sampling at divided by 32
1
Sampling at divided by 4
Low-speed on flag
0
When a SLEEP instruction is executed in high-speed mode or
medium-speed mode, a transition is made to sleep mode, software
standby mode, or watch mode*
When a SLEEP instruction is executed in subactive mode, a transition
is made to watch mode, or directly to high-speed mode
After watch mode is cleared, a transition is made to high-speed mode
1
When a SLEEP instruction is executed in high-speed mode a
transition is made to watch mode or subactive mode*
When a SLEEP instruction is executed in subactive mode, a transition
is made to subsleep mode or watch mode
After watch mode is cleared, a transition is made to subactive mode
Direct-transfer on flag
0
When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode, software standby mode, or watch mode*
When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode or watch mode
1
When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made directly to subactive mode*, or a transition is made to sleep mode
or software standby mode
When a SLEEP instruction is executed in subactive mode, a transition is made directly
to high-speed mode, or a transition is made to subsleep mode
Note: * When a transition is made to watch mode or subactive mode,
high-speed mode must be set.
Note: * When a transition is made to watch mode or subactive mode, high-speed mode must
be set.