383
15.1.4
Register Configuration
The SCI has the internal registers shown in table 15.2. These registers are used to specify
asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the
transmitter/receiver.
Table 15.2 SCI Registers
Channel
Name
Abbreviation
R/W
Initial Value Address*
1
0
Serial mode register 0
SMR0
R/W
H'00
H'FFD8*
3
Bit rate register 0
BRR0
R/W
H'FF
H'FFD9*
3
Serial control register 0
SCR0
R/W
H'00
H'FFDA
Transmit data register 0
TDR0
R/W
H'FF
H'FFDB
Serial status register 0
SSR0
R/(W)*
2
H'84
H'FFDC
Receive data register 0
RDR0
R
H'00
H'FFDD
Serial interface mode register 0 SCMR0
R/W
H'F2
H'FFDE*
3
1
Serial mode register 1
SMR1
R/W
H'00
H'FF88*
3
Bit rate register 1
BRR1
R/W
H'FF
H'FF89*
3
Serial control register 1
SCR1
R/W
H'00
H'FF8A
Transmit data register 1
TDR1
R/W
H'FF
H'FF8B
Serial status register 1
SSR1
R/(W)*
2
H'84
H'FF8C
Receive data register 1
RDR1
R
H'00
H'FF8D
Serial interface mode register 1 SCMR1
R/W
H'F2
H'FF8E*
3
2
Serial mode register 2
SMR2
R/W
H'00
H'FFA0*
3
Bit rate register 2
BRR2
R/W
H'FF
H'FFA1*
3
Serial control register 2
SCR2
R/W
H'00
H'FFA2
Transmit data register 2
TDR2
R/W
H'FF
H'FFA3
Serial status register 2
SSR2
R/(W)*
2
H'84
H'FFA4
Receive data register 2
RDR2
R
H'00
H'FFA5
Serial interface mode register 2 SCMR2
R/W
H'F2
H'FFA6*
3
Keyboard comparator control
register
KBCOMP
R/W
H'00
H'FEE4
Common
Module stop control register
MSTPCRH
R/W
H'3F
H'FF86
MSTPCRL
R/W
H'FF
H'FF87
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, to clear flags.
3. Some serial communication interface registers are assigned to the same addresses as
other registers. In this case, register selection is performed by the IICE bit in the serial
timer control register (STCR).