483
SDA
(master output)
SDA
(slave output)
2
1
23
1
4
36
58
79
Bit 7
Bit 6
Bit 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRIC
ICDRT
ICDRS
TDRE
SCL
(master output)
Interrupt
request
generation
Data 2
Data 1
[6] ICDR write
ICDR write
[6] ICDR write
[6] IRIC clearance
User processing
Data 1
Data 2
Data 3
Data 2
[7]
A
Figure 16.7 Example of Master Transmit Mode Continuous Transmit Operation Timing
(MLS = WAIT = 0)
16.3.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data, and returns
an acknowledge signal. The slave device transmits data. The reception procedure and operations
in master receive mode are described below.
[1] Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Also clear the
ACKB bit in ICSR to 0 (acknowledge data setting).
[2] When ICDR is read (dummy data read), reception is started, and the receive clock is output,
and data received, in synchronization with the internal clock. In order to determine the end of
reception, the IRIC flag in ICCR must be cleared beforehand.
[3] The master device drives SDA at the 9th receive clock pulse to return an acknowledge
signal. When one frame of data has been received, the IRIC flag in ICCR is set to 1 at the
rise of the 9th receive clock pulse. If the IEIC bit in ICCR has been set to 1, an interrupt
request is sent to the CPU. If the RDRF internal flag has been cleared to 0, it is set to 1, and
the receive operation continues. If reception of the next frame ends before the ICDR
read/IRIC flag clearing in [4] is performed, SCL is automatically fixed low in
synchronization with the internal clock.
[4] Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0.