117
Instruction
fetch
NOP
execution
NOP
execution
NOP
execution
Interrupt exception handling
Instruction
fetch
Instruction
fetch
Instruction
fetch
Instruction
fetch
Internal
operation
Stack save
Vector
fetch
Internal
operation
Instruction
fetch
H'0310
H'0312
H'0314
H'0316
H'0318
SP-2
SP-4
H'0036
H'0310 NOP
H'0312 NOP
H'0314 NOP
H'0316 NOP
Breakpoint
NOP instruction is executed at breakpoint address H'0312 and
next address, H'0314; fetch from address H'0316 starts after
end of exception handling.
Instruction
fetch
NOP
execution
MOV.W
execution
Interrupt exception handling
Instruction
fetch
Instruction
fetch
Instruction
fetch
Instruction
fetch
Internal
operation
Stack save
Vector
fetch
Internal
operation
Instruction
fetch
H'0310
H'0312
H'0314
H'0316
H'0318
SP-2
SP-4
H'0036
H'0310 NOP
H'0312 MOV.W
H'0316 NOP
H'0318 NOP
Breakpoint
MOV instruction is executed at breakpoint address H'0312,
NOP instruction at next address, H'0316, is not executed;
fetch from address H'0316 starts after end of exception handling.
#xx:16,Rd
Instruction
fetch
NOP
execution
Interrupt exception handling
Instruction
fetch
Instruction
fetch
Internal
operation
Stack save
Vector
fetch
Internal
operation
H'0310
H'0312
H'0314
SP-2
SP-4
H'0036
H'0310 NOP
H'0312 NOP
H'0314 NOP
H'0316 NOP
Breakpoint
NOP instruction at breakpoint address H'0312 is not executed;
fetch from address H'0312 starts after end of exception handling.
Address bus
Break request
signal
Address bus
Break request
signal
Address bus
Break request
signal
Program area in on-chip memory, 1-state execution instruction at specified break address
Program area in on-chip memory, 2-state execution instruction at specified break address
Program area in external memory (2-state access, 16-bit-bus access),
1-state execution instruction at specified break address
Figure 5.6 Examples of Address Break Timing