参数资料
型号: HMC703LP4E
厂商: Hittite Microwave Corporation
文件页数: 23/58页
文件大小: 0K
描述: IC FRACT-N PLL W/SWEEPR 24QFN
标准包装: 1
类型: 整数 N/小数 N 分频
PLL:
输入: CMOS
输出: CMOS
电路数: 1
比率 - 输入:输出: 1:1
差分 - 输入:输出: 是/无
频率 - 最大: 8GHz
除法器/乘法器: 是/无
电源电压: 3.3V,5V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-VQFN 裸露焊盘
供应商设备封装: 24-QFN 裸露焊盘(4x4)
包装: 标准包装
其它名称: 1127-1065-6
P
LL
s
-
s
M
T
6 - 3
HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 978-250-3373 fax Order On-line at www.hittite.com
Application Support: pll@hittite.com
Parameter
Conditions
Min.
Typ.
Max.
Units
PHAsE NOIsE [14]
Flicker Figure of Merit (FOM)[2]
-270
dBc/Hz
Floor Figure of Merit [11]
Integer HiK Mode
Integer Normal Mode
Fractional HiK Mode [3]
Fractional Normal Mode [3]
-236
-232
-228
-233
-230
-227
-231
-228
-227
-225
dBc/Hz
Flicker Noise at foffset
PNflick = Flicker FOM +20log(fvco) -10log(foffset)
dBc/Hz
Phase Noise Floor at fvco with fpd
PNfloor = Floor FOM + 10log(fpd) +20log(fvco/fpd)
dBc/Hz
VCO referred Phase Noise Contribution
of the PLL vs foffset, fvco, fpd
PN = 10log(10(PNflick /10) + 10(PNfloor /10) )
dBc/Hz
Jitter
ssB 100Hz to 100MHz with
HMC508LP5E VCO
50
fs
sPURIOUs
[4][5]
Integer Boundary spurs @~8GHz
offsets less than loop band-
width, fpd = 50MHz
-60
-52
dBc
LOGIC INPUTs
switching Theshold (Vsw)
VIH/VIL within 50 mV of Vsw
38
47
54
% VDDIO
LOGIC OUTPUT
VOH Output High Voltage
VDDIO
V
VOL Output Low Voltage
0
V
Output impedance : Pull Up
VDDIO=3.3 V
115
150
180
Ohm
Output impedance : Pull Dn
VDDIO=3.3 V
130
135
210
Ohm
DC load
1.5
mA
Digital Output Driver Delay
sCK to Digital Output Delay
1.7nsec with a 3 pF load
0.5ns+0.2ns/pF
8.2ns+0.2ns/pF
ns
RF Divider Range
>4GHz Integer Mode
16 bit , Even values only
32
131,070
< 4GHz Integer Mode
16 bit , All values
16
65,535
> 4GHz Fractional Mode
16 bit
40.0
131,065.0
< 4GHz Fractional Mode
16 bit
20.0
65,531.0
[1] Frequency is guaranteed across process, voltage and temperature from -400C to 850C.
[2] With high charge-pump current, +12dBm 100MHz sine reference
[3] Fractional FOM degrades about 3dB/octave for prescaler input frequencies below 2GHz
[4] Using 50MHz reference with VCO tuned to within one loop bandwidth of an integer multiple of the PD frequency. Larger
offsets produce better results. see the “spurious Performance” section for more information.
[5] Measured with the HMC703LP4E evaluation board. Board design and isolation will affect performance.
[6] Internal divide-by-2 should be enabled for frequencies >4GHz
[7] At low RF Frequency, Rise and fall times should be less than 1ns to maintain performance
[8] slew rate of greater or equal to 0.5 V/ns
[9] Current consumption depends upon operating mode and frequency of the VCO. Typical values are for fractional mode.
[10] Reference input disconnected
[11] Min/Max versus temperature and supply, under typical reference & RF frequencies and power levels
[12] slew > 0.5V/ns is recommended , see Table 7, Figure 5, Figure 6 for more information.
[13] Operable with reduced spectral performance outside of this range.
[14] This section specifies the Phase Noise contribution of the PLL, solution phase noise with a given VCO, loop filter and
reference requires a closed loop calculation using Hittite PLL Design Tool.
[15] As measured on HMC703LP4E Evaluation board, with 100Ohm external termination.
table 34. electrical specifications (Continued)
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