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| 型号： | HMC703LP4E |
| 厂商： | Hittite Microwave Corporation |
| 文件页数： | 31/58页 |
| 文件大小： | 0K |
| 描述： | IC FRACT-N PLL W/SWEEPR 24QFN |
| 标准包装： | 1 |
| 类型： | 整数 N/小数 N 分频 |
| PLL： | 是 |
| 输入： | CMOS |
| 输出： | CMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:1 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 8GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.3V，5V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN 裸露焊盘（4x4） |
| 包装： | 标准包装 |
| 其它名称： | 1127-1065-6 |
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HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 978-250-3373 fax Order On-line at www.hittite.com
Application Support: pll@hittite.com
General Purpose output (GPo) Pin
The PLL shares the LD_sDO (Lock-Detect/serial Data Out) pin to perform various functions. While the pin is most
commonly used to read back registers from chip via the sPI, it is also capable of exporting a variety of interesting
signals and real time test waveforms (including Lock Detect). It is driven by a tri-state CMOs driver with ~200 Ω Rout.
It has logic associated with it to dynamically select whether the driver is enabled, and to decide which data to export
from the chip.
In its default configuration, after power-on-reset, the output driver is disabled, and only drives during appropriately
addressed sPI reads. This allows it to share the output with other devices on the same bus.
Depending on the sPI mode, the read section of sPI cycle is recognized differently
HMC sPI Mode: The driver is enabled during the last 24 bits of sPI READ cycle (not during write cycles).
Open sPI Mode: The driver is enabled if the chip is addressed - ie. The last 3 bits of sPI cycle = ‘000’b before the
rising edge of sEN (Note A).
To consistently monitor any of the GPO signals, including Lock Detect, set Reg 0Fh[7] = 1 to keep the sDO driver
always on. This stops the LDO driver from tri-stating and means that the sDO line cannot be shared with other devices.
The chip will naturally switch away from the GPO data and export the sDO during an sPI read (Note B). To prevent
this automatic data selection, and always select the GPO signal, set “Prevent AutoMux of sDO” (Reg 0Fh[6] = 1). The
phase noise performance at this output is poor and uncharacterized. Also, the GPO output should not be toggling
during normal operation. Otherwise the spectral performance may degrade.
Note that there are additional controls available, which may be helpful if sharing the bus with other devices:
To allow the driver to be active (subject to the conditions above) even when the chip is disabled -
set Reg 01h[7] = 1.
To disable the driver completely, set Reg 08h[5] = 0 (it takes precedence over all else).
To disable either the pull-up or pull-down sections of the driver, Reg 0Fh[8] = 0 or Reg 0Fh[9] = 0 respectively.
Note A: If SEN rises before SCK has clocked in an ‘invalid’ (non-zero) chip -address, the part will start to drive the
bus.
Note B: In Open Mode, the active portion of the read is defined between the 1st SCK rising edge after SEN, to the
next rising edge of SEN.
Example scenarios:
Drive sDO during reads, tri-state otherwise (to allow bus-sharing)
No action required.
Drive sDO during reads, Lock Detect otherwise
set GPO select Reg 0Fh[4:0] = ‘00001’ (which is default)
set “Prevent GPO driver disable” (Reg 0Fh[7] = 1)
Always drive Lock Detect
set “ Prevent AutoMux of sDO” Reg 0Fh[6] = 1
set GPO select Reg 0Fh[4:0]= 00001 (which is default)
set “Prevent GPO driver disable” (Reg 0Fh[7] = 1))
The signals available on the GPO are selected by changing “GPO select”, Reg 0Fh[4:0].
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