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参数资料
型号： IDT82V3280PF
厂商： INTEGRATED DEVICE TECHNOLOGY INC
元件分类： 通信及网络
英文描述： WAN PLL
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封装： TQFP-100
文件页数： 16/167页
文件大小： 1039K
代理商： IDT82V3280PF
IDT82V3280
WAN PLL
Pin Description
16
June 19, 2006
A0 / SDI
A1 / CLKE
A2
A3
A4
A5
A6
69
68
67
66
65
64
63
I
pull-down
CMOS
A[6:0]: Address Bus
In ERPOM, Intel and Motorola modes, these pins are the address bus of the microprocessor
interface.
SDI: Serial Data Input
In Serial mode, this pin is used as the serial data input. Address and data on this pin are seri-
ally clocked into the device on the rising edge of SCLK.
CLKE: SCLK Active Edge Selection
In Serial mode, this pin selects the active edge of SCLK to update the SDO:
High - The falling edge;
Low - The rising edge.
In Multiplexed mode, A0/SDI, A1/CLKE and A[6:2] pins should be connected to ground.
In Serial mode, A[6:2] pins should be connected to ground.
AD[7:0]: Address / Data Bus
In EPROM, Intel and Motorola modes, these pins are the bi-directional data bus of the micro-
processor interface.
In Multiplexed mode, these pins are the bi-directional address/data bus of the microproces-
sor interface.
AD0 / SDO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
83
82
81
80
79
78
77
76
I/O
pull-down
CMOS
SDO: Serial Data Output
In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked
out of the device on the active edge of SCLK.
In Serial mode, AD[7:1] pins should be connected to ground.
WR
71
I
pull-up
CMOS
WR
: Write Operation
In Multiplexed and Intel modes, this pin is asserted low to initiate a write operation.
In Motorola mode, this pin is asserted low to initiate a write operation or s asserted high to ini-
tiate a read operation.
In EPROM and Serial modes, this pin should be connected to ground.
RD
72
I
pull-up
CMOS
RD
: Read Operation
In Multiplexed and Intel modes, this pin is asserted low to initiate a read operation.
In EPROM, Motorola and Serial modes, this pin should be connected to ground.
ALE: Address Latch Enable
In Multiplexed mode, the address on AD[7:0] pins is sampled into the device on the falling
edge of ALE.
ALE / SCLK
73
I
pull-down
CMOS
SCLK: Shift Clock
In Serial mode, a shift clock is input on this pin.
Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated
on the active edge of SCLK. The active edge is determined by the CLKE.
In EPROM, Intel and Motorola modes, this pin should be connected to ground.
Table 1: Pin Description (Continued)
Name
Pin No.
I/O
Type
Description
1
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IDT82V3280PFBLANK 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL
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IDT82V3280PFG8 功能描述:IC PLL WAN SE STRATUM 2 100-TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT
IDT82V3280PFGBLANK 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL
IDT82V3285 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL
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