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参数资料
型号： IDT82V3280PF
厂商： INTEGRATED DEVICE TECHNOLOGY INC
元件分类： 通信及网络
英文描述： WAN PLL
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封装： TQFP-100
文件页数： 69/167页
文件大小： 1039K
代理商： IDT82V3280PF
IDT82V3280
WAN PLL
Programming Information
69
June 19, 2006
INPUT_MODE_CNFG - Input Mode Configuration
Address: 09H
Type: Read / Write
Default Value: 10100XX0
Bit
Name
Description
7
AUTO_EXT_SYNC_EN Refer to the description of the EXT_SYNC_EN bit (b6, 09H).
This bit, together with the AUTO_EXT_SYNC_EN bit (b7, 09H), determines whether EX_SYNC1 is enabled to synchronize
the frame sync output signals.
6
EXT_SYNC_EN
5
PH_ALARM_TIMEOUT
This bit determines how to clear the phase lock alarm.
0: The phase lock alarm will be cleared when a ‘1’ is written to the corresponding INn_PH_LOCK_ALARM bit (b4/0,
43H~49H).
1: The phase lock alarm will be cleared after a period (
= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0]
(b7~6, 08H) in second
) which starts from when the alarm is raised. (default)
These bits set the frequency of the frame sync signal input on the EX_SYNC1 pin.
00: 8 kHz (default)
01: 8 kHz.
10: 4 kHz.
11: 2 kHz.
This bit selects the SDH or SONET network type.
0: SDH. The DPLL required clock is 2.048 MHz when the IN_FREQ[3:0] bits (b3~0, 14H~17H & 19H~22H) are ‘0001’; the
T0/T4 DPLL output from the 16E1/16T1 path is 16E1; and OUT9 outputs a 2.048 MHz signal if enabled.
1: SONET. The DPLL required clock is 1.544 MHz when the IN_FREQ[3:0] bits (b3~0, 14H~17H & 19H~22H) are ‘0001’; the
T0/T4 DPLL output from the 16E1/16T1 path is 16T1; and OUT9 outputs a 1.544 MHz signal if enabled.
The default value of this bit is determined by the SONET/
SDH
pin during reset.
This bit is read only. It indicates the value of the MS/
SL
pin.
Its default value is determined by the MS/
SL
pin during reset.
This bit selects Revertive or Non-Revertive switch for T0 path.
0: Non-Revertive switch. (default)
1: Revertive switch.
4 - 3
SYNC_FREQ[1:0]
2
IN_SONET_SDH
1
MASTER_SLAVE
0
REVERTIVE_MODE
7
6
5
4
3
2
1
0
AUTO_EXT_SY
NC_EN
EXT_SYNC_EN
PH_ALARM_TI
MEOUT
SYNC_FREQ1
SYNC_FREQ0
IN_SONET_SD
H
MASTER_SLAV
E
REVERTIVE_M
ODE
AUTO_EXT_SYNC_EN
EXT_SYNC_EN
Synchronization
don’t-care
0
1
0
1
1
Disabled (default)
Enabled
Enabled if the T0 selected input clock is IN11; otherwise, disabled.
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IDT82V3280PFBLANK 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL
IDT82V3280PFG 功能描述:IC PLL WAN SE STRATUM 2 100-TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT
IDT82V3280PFG8 功能描述:IC PLL WAN SE STRATUM 2 100-TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT
IDT82V3280PFGBLANK 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL
IDT82V3285 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL
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