参数资料
型号: IDT82V3280PF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 通信及网络
英文描述: WAN PLL
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP100
封装: TQFP-100
文件页数: 60/167页
文件大小: 1039K
代理商: IDT82V3280PF
IDT82V3280
WAN PLL
Programming Information
60
June 19, 2006
0B
MON_SW_PBO_CNFG - Frequency
Monitor, Input Clock Selection & PBO
Control
MS_SL_CTRL_CNFG - Master Slave
Control
PROTECTION_CNFG - Register Pro-
tection Mode Configuration
MPU_SEL_CNFG - Microprocessor
Interface Mode Configuration
FREQ_MO
N_CLK
LOS_FLA
G_TO_TD
O
ULTR_FAS
T_SW
EXT_SW
PBO_FRE
Z
PBO_EN
-
FREQ_MO
N_HARD_
EN
MS_SL_C
TRL
P 71
13
-
-
-
-
-
-
-
P 72
7E
PROTECTION_DATA[7:0]
P 72
7F
-
-
-
-
-
MPU_SEL_CNFG[2:0]
P 73
Interrupt Registers
0C
INTERRUPT_CNFG - Interrupt Config-
uration
INTERRUPTS1_STS - Interrupt Status
1
-
-
-
-
-
-
HZ_EN
INT_POL
P 74
0D
IN[8:1]
P 74
0E
INTERRUPTS2_STS - Interrupt Status
2
T0_OPER
ATING_MO
DE
EX_SYNC
_ALARM
T0_MAIN_
REF_FAIL
ED
IN[14:9]
P 75
0F
INTERRUPTS3_STS - Interrupt Status
3
INTERRUPTS1_ENABLE_CNFG
Interrupt Control 1
T4_STS
-
INPUT_TO
_T4
AMI2_VIO
L
AMI2_LOS
AMI1_VIO
L
AMI1_LOS
P 76
10
-
IN[8:1]
P 77
11
INTERRUPTS2_ENABLE_CNFG
Interrupt Control 2
-
T0_OPER
ATING_MO
DE
EX_SYNC
_ALARM
Input Clock Frequency & Priority Configuration Registers
400HZ_SE
L
400HZ_SE
L
DIRECT_D
IV
DIRECT_D
IV
T0_MAIN_
REF_FAIL
ED
IN[14:9]
P 77
12
INTERRUPTS3_ENABLE_CNFG
Interrupt Control 3
-
T4_STS
-
INPUT_TO
_T4
AMI2_VIO
L
AMI2_LOS
AMI1_VIO
L
AMI1_LOS
P 78
14
IN1_CNFG - Input Clock 1 Configura-
tion
IN2_CNFG - Input Clock 2 Configura-
tion
IN3_CNFG - Input Clock 3 Configura-
tion
IN4_CNFG - Input Clock 4 Configura-
tion
IN5_IN6_HF_DIV_CNFG - Input Clock
5 & 6 High Frequency Divider Configu-
ration
IN5_CNFG - Input Clock 5 Configura-
tion
IN6_CNFG - Input Clock 6 Configura-
tion
IN7_CNFG - Input Clock 7 Configura-
tion
IN8_CNFG - Input Clock 8 Configura-
tion
IN9_CNFG - Input Clock 9 Configura-
tion
IN10_CNFG - Input Clock 10 Configu-
ration
-
BUCKET_SEL[1:0]
IN_FREQ[3:0]
P 79
15
-
BUCKET_SEL[1:0]
IN_FREQ[3:0]
P 79
16
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
P 80
17
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
P 81
18
IN6_DIV[1:0]
-
-
-
-
IN5_DIV[1:0]
P 82
19
DIRECT_D
IV
DIRECT_D
IV
DIRECT_D
IV
DIRECT_D
IV
DIRECT_D
IV
DIRECT_D
IV
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
P 83
1A
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
P 84
1B
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
P 85
1C
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
P 86
1D
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
P 87
1E
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
P 88
Table 42: Register List and Map (Continued)
Address
(Hex)
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reference
Page
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