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参数资料
型号： IDT82V3280PF
厂商： INTEGRATED DEVICE TECHNOLOGY INC
元件分类： 通信及网络
英文描述： WAN PLL
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封装： TQFP-100
文件页数： 34/167页
文件大小： 1039K
代理商： IDT82V3280PF
IDT82V3280
WAN PLL
Functional Description
34
June 19, 2006
3.10
T0 / T4 DPLL OPERATING MODE
The T0/T4 DPLL gives a stable performance in different applications
without being affected by operating conditions or silicon process varia-
tions. It integrates a PFD (Phase & Frequency Detector), a LPF (Low
Pass Filter) and a DCO (Digital Controlled Oscillator), which forms a
closed loop. If no input clock is selected, the loop is not closed, and the
PFD and LPF do not function.
The PFD detects the phase error, including the fast loss, coarse
phase loss and fine phase loss (refer to
Chapter 3.7.1.1 Fast Loss
to
Chapter 3.7.1.3 Fine Phase Loss
). The averaged phase error of the T0/
T4 DPLL feedback with respect to the selected input clock is indicated
by the CURRENT_PH_DATA[15:0] bits. It can be calculated as follows:
Averaged Phase Error (ns) = CURRENT_PH_DATA[15:0] X 0.61
The LPF filters jitters. Its 3 dB bandwidth and damping factor are pro-
grammable. A range of bandwidths and damping factors can be set to
meet different application requirements. Generally, the lower the damp-
ing factor is, the longer the locking time is and the more the gain is.
The DCO controls the DPLL output. The frequency of the DPLL out-
put is always multiplied on the basis of the master clock. The phase and
frequency offset of the DPLL output may be locked to those of the
selected input clock. The current frequency offset with respect to the
master clock is indicated by the CURRENT_DPLL_FREQ[23:0] bits, and
can be calculated as follows:
Current Frequency Offset (ppm) = CURRENT_DPLL_FREQ[23:0] X
0.000011
3.10.1
T0 DPLL OPERATING MODE
The T0 DPLL loop is closed except in Free-Run mode and Holdover
mode.
For a closed loop, different bandwidths and damping factors can be
used depending on DPLL locking stages: starting, acquisition and
locked.
In the first two seconds when the T0 DPLL attempts to lock to the
selected input clock, the starting bandwidth and damping factor are
used. They are set by the T0_DPLL_START_BW[4:0] bits and the
T0_DPLL_START_DAMPING[2:0] bits respectively.
During the acquisition, the acquisition bandwidth and damping factor
are used. They are set by the T0_DPLL_ACQ_BW[4:0] bits and the
T0_DPLL_ACQ_DAMPING[2:0] bits respectively.
When the T0 selected input clock is locked, the locked bandwidth
and
damping
factor
are
used.
T0_DPLL_LOCKED_BW[4:0]
T0_DPLL_LOCKED_DAMPING[2:0] bits respectively.
They
bits
are
set
by
the
the
and
The corresponding bandwidth and damping factor are used when the
T0 DPLL operates in different DPLL locking stages: starting, acquisition
and locked, as controlled by the device automatically.
Only the locked bandwidth and damping factor can be used regard-
less of the T0 DPLL locking stage, as controlled by the AUTO_BW_SEL
bit.
3.10.1.1
Free-Run Mode
In Free-Run mode, the T0 DPLL output refers to the master clock
and is not affected by any input clock. The accuracy of the T0 DPLL out-
put is equal to that of the master clock.
3.10.1.2
Pre-Locked Mode
In Pre-Locked mode, the T0 DPLL output attempts to track the
selected input clock.
The Pre-Locked mode is a secondary, temporary mode.
3.10.1.3
Locked Mode
In Locked mode, the T0 selected input clock is locked. The phase
and frequency offset of the T0 DPLL output track those of the T0
selected input clock.
In this mode, if the T0 selected input clock is in fast loss status and
the FAST_LOS_SW bit is ‘1’, the T0 DPLL is unlocked (refer to
Chapter 3.7.1.1 Fast Loss
) and will enter Lost-Phase mode when the
operating mode is switched automatically; if the T0 selected input clock
is in fast loss status and the FAST_LOS_SW bit is ‘0’, the T0 DPLL lock-
ing status is not affected and the T0 DPLL will enter Temp-Holdover
mode automatically.
3.10.1.3.1 Temp-Holdover Mode
The T0 DPLL will automatically enter Temp-Holdover mode with a
selected input clock switch or no qualified input clock available when the
operating mode switch is under external control.
In Temp-Holdover mode, the T0 DPLL has temporarily lost the
selected input clock. The T0 DPLL operation in Temp-Holdover mode
and that in Holdover mode are alike (refer to
Chapter 3.10.1.5 Holdover
Mode
) except the frequency offset acquiring methods. See
Chapter 3.10.1.5 Holdover Mode
for details about the methods. The
method is selected by the TEMP_HOLDOVER_MODE[1:0] bits, as
shown in
Table 18
:
The device automatically controls the T0 DPLL to exit from Temp-
Holdover mode.
3.10.1.4
Lost-Phase Mode
In Lost-Phase mode, the T0 DPLL output attempts to track the
selected input clock.
The Lost-Phase mode is a secondary, temporary mode.
3.10.1.5
Holdover Mode
In Holdover mode, the T0 DPLL resorts to the stored frequency data
acquired in Locked mode to control its output. The T0 DPLL output is not
Table 18: Frequency Offset Control in Temp-Holdover Mode
TEMP_HOLDOVER_MODE[1:0]
Frequency Offset Acquiring Method
00
01
10
11
the same as that used in Holdover mode
Automatic Instantaneous
Automatic Fast Averaged
Automatic Slow Averaged
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相关代理商/技术参数
参数描述
IDT82V3280PFBLANK 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL
IDT82V3280PFG 功能描述:IC PLL WAN SE STRATUM 2 100-TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT
IDT82V3280PFG8 功能描述:IC PLL WAN SE STRATUM 2 100-TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT
IDT82V3280PFGBLANK 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL
IDT82V3285 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL
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