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| 型号： | IS61VPS51218A-250B3 |
| 厂商： | INTEGRATED SILICON SOLUTION INC |
| 元件分类： | SRAM |
| 英文描述： | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| 中文描述： | 512K X 18 CACHE SRAM, 2.6 ns, PBGA165 |
| 封装： | 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165 |
| 文件页数： | 15/35页 |
| 文件大小： | 562K |
| 代理商： | IS61VPS51218A-250B3 |
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Integrated Silicon Solution, Inc.
Rev. I
01/13/09
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
TEST DATA OUT (TDO)
TheTDOoutputpinisusedtoseriallyclockdata-outfrom
theregisters.Theoutputisactivedependingonthecurrent
state of the TAP state machine (see TAP Controller State
Diagram).TheoutputchangesonthefallingedgeofTCK
andTDOisconnectedtotheLeastSignificantBit(LSB)
of any register.
PERFORMINg A TAP RESET
AResetisperformedbyforcingTMSHIGH(Vdd) for five
risingedgesofTCK.RESETmaybeperformedwhilethe
SRAMisoperatinganddoesnotaffectitsoperation.At
power-up,theTAPisinternallyresettoensurethatTDO
comesupinahigh-Zstate.
TAP REgISTERS
RegistersareconnectedbetweentheTDIandTDOpins
andallowdatatobescannedintoandoutoftheSRAM
test circuitry
. Onlyoneregistercanbeselectedatatime
throughtheinstructionregisters.Dataisseriallyloaded
intotheTDIpinontherisingedgeofTCKandoutputon
theTDOpinonthefallingedgeofTCK.
Instruction Register
Three-bitinstructionscanbeseriallyloadedintothein-
structionregister.Thisregisterisloadedwhenitisplaced
between the TDI and TDO pins. (See TAPControllerBlock
Diagram) Atpower-up,theinstructionregisterisloaded
with the IDCODE instruction. It is also loaded with the
IDCODEinstructionifthecontrollerisplacedinareset
state as previously described.
WhentheTAPcontrollerisintheCaptureIRstate,thetwo
leastsignificantbitsareloadedwithabinary“01”patternto
allow for fault isolation of the board level serial test path.
Bypass Register
Tosavetimewhenseriallyshiftingdatathroughregisters,
itissometimesadvantageoustoskipcertainstates.The
bypassregisterisasingle-bitregisterthatcanbeplaced
betweenTDIandTDOpins.Thisallowsdatatobeshifted
through the SRAM with minimal delay.The bypass reg-
isterissetLOW(Vss)whentheBYPASSinstructionis
executed.
Boundary Scan Register
Theboundaryscanregisterisconnectedtoallinputand
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
densitydevices.Thex36configurationhasa75-bit-long
registerandthex18configurationalsohasa75-bit-long
register.The boundary scan register is loaded with the
contentsoftheRAMInputandOutputringwhentheTAP
controllerisintheCapture-DRstateandthenplacedbe-
tween the TDI and TDO pins when the controller is moved
to the Shift-DRstate.TheEXTEST,SAMPLE/PRELOAD
andSAMPLE-Zinstructionscanbeusedtocapturethe
contentsoftheInputandOutputring.
TheBoundaryScanOrdertablesshowtheorderinwhich
thebitsareconnected.Eachbitcorrespondstooneofthe
bumpsontheSRAMpackage.TheMSBoftheregisteris
connectedtoTDI,andtheLSBisconnectedtoTDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit
codeduringtheCapture-DRstatewhentheIDCODEcom-
mandisloadedtotheinstructionregister.TheIDCODE
ishardwiredintotheSRAMandcanbeshiftedoutwhen
theTAPcontrollerisintheShift-DRstate.TheIDregister
has vendor code and other information described in the
IdentificationRegisterDefinitionstable.
Scan Register Sizes
Register
Bit Size
Name
(x18)
(x36)
Instruction
3
Bypass
1
ID
32
BoundaryScan
75
IDENTIFICATION REgISTER DEFINITIONS
Instruction Field
Description
256K x 36
512K x 18
RevisionNumber (31:28)
Reservedforversionnumber.
xxxx
DeviceDepth (27:23)
DefinesdepthofSRAM.256Kor512K
00111
01000
DeviceWidth (22:18)
DefineswidthoftheSRAM.x36orx18
00100
00011
ISSIDeviceID (17:12)
Reservedforfutureuse.
xxxxx
ISSIJEDECID (11:1)
AllowsuniqueidentificationofSRAMvendor.
00011010101
00011010101
IDRegisterPresence (0)
IndicatethepresenceofanIDregister.
1
相关PDF资料 |
PDF描述 |
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| IS61VPS51218A-250B3I | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61VPS51218A-250TQ | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61VPS51218A-250TQI | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61VPS51236A-200B2 | 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS62WV10248DBLL-45MLI | 1M X 8 STANDARD SRAM, 45 ns, PBGA48 |
相关代理商/技术参数 |
参数描述 |
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| IS61VPS51232-166TQI | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61VPS51236A-200B3 | 功能描述:静态随机存取存储器 18Mb,Pipeline,Sync,512K x 36,200MHz,2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| IS61VPS51236A-200B3I | 功能描述:静态随机存取存储器 18Mb,Pipeline,Sync,512K x 36,200MHz,2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| IS61VPS51236A-200B3I-TR | 功能描述:静态随机存取存储器 18Mb,Pipeline,Sync,512K x 36,200MHz,2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| IS61VPS51236A-200B3-TR | 功能描述:静态随机存取存储器 18Mb,Pipeline,Sync,512K x 36,200MHz,2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
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