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| 型号： | IS61VPS51218A-250B3 |
| 厂商： | INTEGRATED SILICON SOLUTION INC |
| 元件分类： | SRAM |
| 英文描述： | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| 中文描述： | 512K X 18 CACHE SRAM, 2.6 ns, PBGA165 |
| 封装： | 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165 |
| 文件页数： | 16/35页 |
| 文件大小： | 562K |
| 代理商： | IS61VPS51218A-250B3 |
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Integrated Silicon Solution, Inc.
23
Rev. I
01/13/09
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
TAP INSTRUCTION SET
Eightinstructionsarepossiblewiththethree-bitinstruction
register and all combinations are listed in the Instruction
Codetable.Three instructions are listed as RESERVED
and should not be used and the other five instructions are
describedbelow.TheTAPcontrollerusedinthisSRAM
isnotfullycompliantwiththe1149.1conventionbecause
some mandatory instructions are not fully implemented.
TheTAPcontrollercannotbeusedtoloadaddress,dataor
control signals and cannot preload the Input or Output buf-
fers.TheSRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of SAMPLE/
PRELOAD;insteaditperformsacaptureoftheInputs and
Outputringwhentheseinstructionsareexecuted.Instruc-
tionsareloadedintotheTAPcontrollerduringtheShift-IR
statewhentheinstructionregisterisplacedbetweenTDI
andTDO.Duringthisstate,instructionsareshiftedfrom
theinstructionregisterthroughtheTDIandTDOpins.To
executeaninstructiononceitisshiftedin,theTAPcontrol-
lermustbemovedintotheUpdate-IRstate.
ExTEST
EXTESTisamandatory1149.1instructionwhichistobe
executedwhenevertheinstructionregisterisloadedwith
all0s.BecauseEXTESTisnotimplementedintheTAP
controller,thisdeviceisnot1149.1standardcompliant.
TheTAPcontrollerrecognizesanall-0instruction.Whenan
EXTESTinstructionisloadedintotheinstructionregister,
theSRAMrespondsasifaSAMPLE/PRELOADinstruction
hasbeenloaded.Thereisadifferencebetweentheinstruc-
tions, unlike the SAMPLE/PRELOADinstruction,EXTEST
placestheSRAMoutputsinaHigh-Zstate.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-
bit code to be loaded into the instruction register. It also
placestheinstructionregisterbetweentheTDIandTDO
pinsandallowstheIDCODEtobeshiftedoutofthedevice
when theTAP controller enters the Shift-DR state.The
IDCODEinstructionisloadedintotheinstructionregister
uponpower-uporwhenevertheTAPcontrollerisgivena
test logic reset state.
SAMPLE-Z
The SAMPLE-Z instruction causes the boundary scan
registertobeconnectedbetweentheTDIandTDOpins
whentheTAPcontrollerisinaShift-DRstate.Italsoplaces
allSRAMoutputsintoaHigh-Zstate.
SAMPLE/PRELOAD
SAMPLE/PRELOADisa1149.1mandatoryinstruction.The
PRELOADportionofthisinstructionisnotimplemented,so
theTAPcontrollerisnotfully1149.1compliant.Whenthe
SAMPLE/PRELOADinstructionisloadedtotheinstruc-
tionregisterandtheTAPcontrollerisintheCapture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
ItisimportanttorealizethattheTAPcontrollerclockoper-
atesatafrequencyupto10MHz,whiletheSRAMclock
runsmorethananorderofmagnitudefaster.Becauseof
theclockfrequencydifferences,itispossiblethatduring
theCapture-DRstate,aninputoroutputwillunder-goa
transition.TheTAPmayattemptasignalcapturewhilein
transition(metastablestate).Thedevicewillnotbeharmed,
but there is no guarantee of the value that will be captured
or repeatable results.
Toguaranteethattheboundaryscanregisterwillcapture
thecorrectsignalvalue,theSRAMsignalmustbestabilized
longenoughtomeettheTAPcontroller’scaptureset-up
plus hold times (tcs and tch).ToinsurethattheSRAMclock
input is captured correctly, designs need a way to stop (or
slow)theclockduringaSAMPLE/PRELOADinstruction.
If this is not an issue, it is possible to capture all other
signals and simply ignore the value of the CLK captured
in the boundary scan register.
Oncethedataiscaptured,itispossibletoshiftoutthedata
byputtingtheTAPintotheShift-DRstate.Thisplacesthe
boundaryscanregisterbetweentheTDIandTDOpins.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the Update-
DR state while performing a SAMPLE/PRELOAD instruction
willhavethesameeffectasthePause-DRcommand.
BYPASS
When the BYPASS instruction is loaded in the instruc-
tionregisterandtheTAPisplacedinaShift-DRstate,
thebypassregisterisplacedbetweentheTDIandTDO
pins.TheadvantageoftheBYPASSinstructionisthatit
shortens the boundary scan path when multiple devices
are connected together on a board.
RESERVED
Theseinstructionsarenotimplementedbutarereserved
forfutureuse.Donotusetheseinstructions.
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PDF描述 |
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相关代理商/技术参数 |
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| IS61VPS51232-166TQI | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61VPS51236A-200B3 | 功能描述:静态随机存取存储器 18Mb,Pipeline,Sync,512K x 36,200MHz,2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| IS61VPS51236A-200B3I | 功能描述:静态随机存取存储器 18Mb,Pipeline,Sync,512K x 36,200MHz,2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| IS61VPS51236A-200B3I-TR | 功能描述:静态随机存取存储器 18Mb,Pipeline,Sync,512K x 36,200MHz,2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| IS61VPS51236A-200B3-TR | 功能描述:静态随机存取存储器 18Mb,Pipeline,Sync,512K x 36,200MHz,2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
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